[PATCH] arm64: dts: ti: k3-am642-evm: Add ICSSG0 overlay for dual EMAC support
MD Danish Anwar
danishanwar at ti.com
Thu Feb 26 20:53:23 PST 2026
Hi Meghana,
On 26/02/26 5:24 pm, Meghana Malladi wrote:
> Add device tree overlay to enable ICSSG0 dual EMAC support on AM642 EVM.
> This overlay enables all four ICSSG Ethernet interfaces (ICSSG0 port0/1
> and ICSSG1 port0/1) in dual EMAC mode.
Why? Your subject says "Add ICSSG0" but the overlay is adding both
ICSSG0 and ICSSG1. AFAIK, overlay k3-am642-evm-icssg1-dualemac.dtbo
already enables ICSSG1 so why is this overlay again enabling the same?
>
> Signed-off-by: Meghana Malladi <m-malladi at ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 4 +
> .../boot/dts/ti/k3-am642-evm-icssg0-exp.dtso | 265 ++++++++++++++++++
> 2 files changed, 269 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg0-exp.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index ba01a929e06f..458b9d523069 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo
>
> # Boards with AM64x SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg0-exp.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo
> dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-pcie0-ep.dtbo
> @@ -218,6 +219,8 @@ k3-am62p5-sk-csi2-ov5640-dtbs := k3-am62p5-sk.dtb \
> k3-am62x-sk-csi2-ov5640.dtbo
> k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \
> k3-am62x-sk-csi2-tevi-ov5640.dtbo
> +k3-am642-evm-icssg0-exp-dtbs := \
> + k3-am642-evm.dtb k3-am642-evm-icssg0-exp.dtbo
Why have you named the overlay icssg0-exp ? What does exp mean here?
More suitable name would be `k3-am642-evm-icssg0.dtbo`
> k3-am642-evm-icssg1-dualemac-dtbs := \
> k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo
> k3-am642-evm-icssg1-dualemac-mii-dtbs := \
> @@ -306,6 +309,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
> k3-am62p5-sk-csi2-imx219.dtb \
> k3-am62p5-sk-csi2-ov5640.dtb \
> k3-am62p5-sk-csi2-tevi-ov5640.dtb \
> + k3-am642-evm-icssg0-exp.dtb \
> k3-am642-evm-icssg1-dualemac.dtb \
> k3-am642-evm-icssg1-dualemac-mii.dtb \
> k3-am642-evm-pcie0-ep.dtb \
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0-exp.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0-exp.dtso
> new file mode 100644
> index 000000000000..5a8462245704
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0-exp.dtso
> @@ -0,0 +1,265 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/**
> + * DT overlay for enabling ICSSG0 dual EMAC on AM642 EVM with
> + * DP83TG720-IND-SPE-EVM daughter card
> + *
> + * AM642 EVM Product link: https://www.ti.com/tool/TMDS64EVM
> + * DP83TG720 daughter card link: https://www.ti.com/tool/DP83TG720-IND-SPE-EVM
> + *
> + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "k3-pinctrl.h"
> +
> +&{/aliases} {
> + ethernet0 = &icssg0_emac0;
> + ethernet1 = &icssg0_emac1;
> + ethernet2 = "/icssg1-eth/ethernet-ports/port at 0";
> + ethernet3 = "/icssg1-eth/ethernet-ports/port at 1";
> +};
> +
> +&{/} {
> + mdio-mux-2 {
> + compatible = "mdio-mux-multiplexer";
> + mux-controls = <&mdio_mux>;
> + mdio-parent-bus = <&icssg1_mdio>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mdio at 0 {
> + reg = <0x0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg1_phy2: ethernet-phy at 3 {
> + reg = <3>;
> + tx-internal-delay-ps = <250>;
> + rx-internal-delay-ps = <2000>;
> + };
> + };
> + };
> +
> + icssg0_eth: icssg0-eth {
> + compatible = "ti,am642-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pru_icssg0_rgmii1_pins_default>, <&pru_icssg0_rgmii2_pins_default>;
> +
> + sram = <&oc_sram>;
> + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
> + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
> +
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> +
> + ti,mii-g-rt = <&icssg0_mii_g_rt>;
> + ti,mii-rt = <&icssg0_mii_rt>;
> + ti,pa-stats = <&icssg0_pa_stats>;
> + ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
> +
> + interrupt-parent = <&icssg0_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> +
> + dmas = <&main_pktdma 0xc100 0>, /* egress slice 0 */
> + <&main_pktdma 0xc101 0>, /* egress slice 0 */
> + <&main_pktdma 0xc102 0>, /* egress slice 0 */
> + <&main_pktdma 0xc103 0>, /* egress slice 0 */
> + <&main_pktdma 0xc104 0>, /* egress slice 1 */
> + <&main_pktdma 0xc105 0>, /* egress slice 1 */
> + <&main_pktdma 0xc106 0>, /* egress slice 1 */
> + <&main_pktdma 0xc107 0>, /* egress slice 1 */
> + <&main_pktdma 0x4100 0>, /* ingress slice 0 */
> + <&main_pktdma 0x4101 0>, /* ingress slice 1 */
> + <&main_pktdma 0x4102 0>, /* mgmnt rsp slice 0 */
> + <&main_pktdma 0x4103 0>; /* mgmnt rsp slice 1 */
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1",
> + "rxmgm0", "rxmgm1";
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg0_emac0: port at 0 {
> + reg = <0>;
> + phy-handle = <&icssg0_phy00>;
> + phy-mode = "rgmii-id";
> + syscon-rgmii-delay = <&main_conf 0x4100>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> +
> + icssg0_emac1: port at 1 {
> + reg = <1>;
> + phy-handle = <&icssg0_phy01>;
> + phy-mode = "rgmii-id";
> + syscon-rgmii-delay = <&main_conf 0x4104>;
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +};
> +
> +&main_pmx0 {
> + pru_icssg0_mdio_pins_default: pru-icssg0-mdio-pins-default {
> + pinctrl-single,pins = <
> + /* (P3) PRG0_MDIO0_MDC */
> + AM64X_IOPAD(0x0204, PIN_OUTPUT, 0)
> + /* (P2) PRG0_MDIO0_MDIO */
> + AM64X_IOPAD(0x0200, PIN_INPUT, 0)
> + /* (P16) GPIO0_32 - GPMC0_ADVn_ALE - GPIO_ETH0/1_RESETn# */
> + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7)
> + >;
> + };
> +
> + pru_icssg0_rgmii1_pins_default: pru-icssg0-rgmii1-pins-default {
> + pinctrl-single,pins = <
> + /* (module-sitara) */
> + /* (a14-y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
> + AM64X_IOPAD(0x0160, PIN_INPUT, 2)
> + /* (b14-r4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
> + AM64X_IOPAD(0x0164, PIN_INPUT, 2)
> + /* (d14-u2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
> + AM64X_IOPAD(0x0168, PIN_INPUT, 2)
> + /* (e14-v2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
> + AM64X_IOPAD(0x016c, PIN_INPUT, 2)
> + /* (e13-t3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
> + AM64X_IOPAD(0x0178, PIN_INPUT, 2)
> + /* (b13-aa2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
> + AM64X_IOPAD(0x0170, PIN_INPUT, 2)
> +
> + /* (a11-y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
> + AM64X_IOPAD(0x018c, PIN_OUTPUT, 2)
> + /* (c11-aa3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
> + AM64X_IOPAD(0x0190, PIN_OUTPUT, 2)
> + /* (d11-r6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
> + AM64X_IOPAD(0x0194, PIN_OUTPUT, 2)
> + /* (b10-v4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
> + AM64X_IOPAD(0x0198, PIN_OUTPUT, 2)
> + /* (e10-u4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
> + AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2)
> + /* (c10-t5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
> + AM64X_IOPAD(0x019c, PIN_OUTPUT, 2)
> + >;
> + };
> +
> + pru_icssg0_rgmii2_pins_default: pru-icssg0-rgmii2-pins-default {
> + pinctrl-single,pins = <
> + /* (e9-y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
> + AM64X_IOPAD(0x01b0, PIN_INPUT, 2)
> + /* (a8-w2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
> + AM64X_IOPAD(0x01b4, PIN_INPUT, 2)
> + /* (c8-v3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
> + AM64X_IOPAD(0x01b8, PIN_INPUT, 2)
> + /* (d8-t4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
> + AM64X_IOPAD(0x01bc, PIN_INPUT, 2)
> + /* (e7-r5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
> + AM64X_IOPAD(0x01c8, PIN_INPUT, 2)
> + /* (b7-w3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
> + AM64X_IOPAD(0x01c0, PIN_INPUT, 2)
> +
> + /* (a5-w4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */
> + AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2)
> + /* (c5-y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */
> + AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2)
> + /* (d5-t6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */
> + AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2)
> + /* (b4-u6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */
> + AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2)
> + /* (a3-aa4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
> + AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2)
> + /* (c4-u5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */
> + AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2)
> + >;
> + };
> +
> + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins {
> + pinctrl-single,pins = <
> + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
> + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
> + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
> + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
> + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
> + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
> + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
> + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
> + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
> + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
> + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
> + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
> + >;
> + };
> +
> + icssg0_iep0_pins_default: icssg0-iep0-pins-default {
> + pinctrl-single,pins = <
> + AM64X_IOPAD(0x01ac, PIN_OUTPUT, 2) /* (W1) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
> + >;
> + };
> +};
> +
> +&cpsw3g {
> + pinctrl-0 = <&rgmii1_pins_default>;
> +};
> +
> +&cpsw_port2 {
> + status = "disabled";
> +};
Why are you disabling cpsw_port2? AFAIK they are not related to ICSSG0.
> +
> +&mdio_mux_1 {
> + status = "disabled";
> +};
> +
> +&icssg0_mdio {
> + pinctrl-names = "default";
> + status = "okay";
> + pinctrl-0 = <&pru_icssg0_mdio_pins_default>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg0_phy00: ethernet-phy at 0 {
> + reg = <0x0>;
> + };
> +
> + icssg0_phy01: ethernet-phy at 1 {
> + reg = <0xA>;
> + };
> +};
> +
> +&icssg0_iep0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&icssg0_iep0_pins_default>;
> +};
> +
> +&icssg1_eth {
> + pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>;
> +};
> +
> +&icssg1_emac1 {
> + status = "okay";
> + phy-handle = <&icssg1_phy2>;
> + phy-mode = "rgmii-id";
> +};
Again this is already taken care in `k3-am642-evm-icssg1-dualemac.dtso`
Your this patch should only enable ICSSG0. If someone needs to enable
both ICSSG0 and ICSSG1 they can apply both of the below overlays.
- k3-am642-evm-icssg1-dualemac.dtbo
- k3-am642-evm-icssg0.dtbo
> +
> +&main_gpio0 {
> + phy-line-hog {
> + gpio-hog;
> + gpios = <32 GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "phy-hog-line";
> + };
> +};
>
> base-commit: 4916f2e2f3fc9aef289fcd07949301e5c29094c2
--
Thanks and Regards,
Danish
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