[PATCH v3] PCI: dw-rockchip: Enable async probe by default

[Niklas Cassel]

On Thu, Feb 26, 2026 at 03:40:23PM +0530, Anand Moon wrote:
> Rockchip DWC PCIe driver currently performs synchronous link training for
> combo PHYs (PCIe 3.0/2.0 and SATA 3.0) during boot. This process waits for
> the link to be fully established, adding several milliseconds to the boot
> sequence. To optimize boot time, this change enables asynchronous probing,
> allowing link establishment to proceed in the background while the kernel
> continues probing other devices.
> 
> Cc: Grimmauld <grimmauld at grimmauld.de>
> Cc: Niklas Cassel <cassel at kernel.org>
> Tested-by: Grimmauld <grimmauld at grimmauld.de>
> Signed-off-by: Anand Moon <linux.amoon at gmail.com>

Reviewed-by: Niklas Cassel <cassel at kernel.org>