[PATCH v8 01/10] dt-bindings: mfd: add support for the NXP SIUL2 module

[Ghennadi Procopciuc]

On 2/23/2026 3:14 PM, Krzysztof Kozlowski wrote:
> On 23/02/2026 12:51, Khristine Andreea Barbulescu wrote:
>> On 2/20/2026 4:41 PM, Krzysztof Kozlowski wrote:
>>> On 20/02/2026 15:36, Khristine Andreea Barbulescu wrote:
>>>> Hello Krzysztof,
>>>>
>>>> On 2/20/2026 12:16 PM, Krzysztof Kozlowski wrote:
>>>>> [You don't often get email from krzk at kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>>
>>>>> On 19/02/2026 12:36, Khristine Andreea Barbulescu wrote:
>>>>>>>
>>>>>>>> +      reg:
>>>>>>>> +        maxItems: 1
>>>>>>>
>>>>>>> You have 'reg' so the node name should have unit-address.
>>>>>>>
>>>>>>> However, there's not any real DT resources in this child node, so you
>>>>>>> should just drop it.
>>>>>>>
>>>>>>
>>>>>> For context, SIUL2 exposes a set of platform‑capability and SoC identification registers that are split across the two discontiguous ranges: SIUL2-0 and SIUL2-1. These registers are the source of SoC information (e.g. identification and capability flags) that other subsystems are expected to consume (e.g. PCI Express). Because those fields are physically divided between the two SIUL2 ranges, consumers need reliable access to both ranges to correctly discover and configure the platform.
>>>>>>
>>>>>> Hence, my proposal is to keep the two 'syscon' child nodes.
>>>>>
>>>>> Please wrap your replies correctly, so this will be easily parseable.
>>>>>
>>>>> I do not understand the reasoning. If you have two register ranges, you
>>>>> have two <reg> entries and having a child node has nothing to do with it.
>>>>>
>>>>
>>>> I’ve reorganized the SIUL2 node with two syscon subnodes for the two
>>>> register regions used to read system info, and a separate
>>>> pinctrl/GPIO child (as discussed in the v8 06/10 thread [0]). The parent
>>>> SIUL2 node now carries the bus addressing and ranges:
>>>
>>> That's not the answer to the comment. Read again:
>>>
>>> 1. Reviewer: No resources, so no separate node.
>>> 2. Your answer: some soc capability and two address spaces
>>> 3. Reviewer: Does not matter, address spaces can go again to original place
>>> 4. Irrelevant reply.
>>>
>>> So again, read the first comment - do you have dedicated resources in
>>> children?
>>>
>>>>  
>>>>     siul2: siul2 at 4009c000 {
>>>>         compatible = "nxp,s32g3-siul2", "nxp,s32g2-siul2";
>>>>         #address-cells = <1>;
>>>>         #size-cells = <1>;
>>>>         ranges = <0x4009c000 0x4009c000 0x179c>,
>>>> 		 <0x44010000 0x44010000 0x17b0>;
>>>>  
>>>>         siul20: siul20 at 4009c000 {
>>>>             compatible = "nxp,s32g-siul2-syscfg", "syscon";
>>>>             reg = <0x4009c000 0x179c>;
>>>
>>> 0x179c is odd size. Looks fake.
>>>
>>>
>>>>         };
>>>>  
>>>>         siul21: siul21 at 44010000 {
>>>>             compatible = "nxp,s32g-siul2-syscfg", "syscon";
>>>
>>> And two same devices with same compatible proof it.
>>>
>>> Best regards,
>>> Krzysztof
>>
>> We don’t have dedicated resources for children. In particular,
> 
> Then previous comments/review stay.
> 
>> there are no resources allocated specifically for nodes like
>> "nxp,s32g-siul2-syscfg". Their consumers are the pinctrl/gpio
>> driver and other drivers that read SoC‑specific information from
>> those shared registers.
>>  
>> My alternative is to keep two separate syscon providers for the
> 
> You got review already.
> 
> Best regards,
> Krzysztof

Hi Krzysztof & Arnd,

I still believe that nvmem is a suitable and accurate mechanism for
describing SoC‑specific identification information, as originally
proposed in [0], assuming the necessary adjustments are made.

More specifically, instead of modeling software-defined cells, the nvmem
layout would describe the actual hardware registers backing this
information. One advantage of this approach is that consumer nodes (for
example PCIe, Ethernet, or other IPs that need SoC identification data)
can reference these registers using the standard nvmem-cells /
nvmem-cell-names mechanism, without introducing custom, per-subsystem
bindings.

Looking at the nvmem binding documentation [1], it appears that
individual fields of identification registers (similar to MIDR) could,
in principle, be exposed using a bits property, for example:

family_letter at 4009c004 {
  reg = <0x4009c004 0x4>;
  bits = <31 26>;
};

That said, an alternative (and arguably more common) approach is to
expose entire registers as fixed-layout cells, and let consumers decode
bitfields in software. Below is an example of how this would look when
embedded in the existing SIUL2 node, without relying on per-field bits
properties:

siul2: pinctrl at 4009c000 {
  compatible = "nxp,s32g2-siul2";
  reg = <0x4009c000 0x2000>,
	<0x44010000 0x2000>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x4009c000 0x4009c000 0xc>,
	   <0x44010000 0x44010000 0xc>;
  reg-names = "siul20", "siul21";
  gpio-controller;
  #gpio-cells = <2>;
  gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>;
  interrupt-controller;
  #interrupt-cells = <2>;
  interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;

  jtag-pins {
	jtag-grp0 {
	  pinmux = <0x0>;
	  input-enable;
	  bias-pull-up;
	  slew-rate = <166>;
	};
  };

  nvmem-layout {
	compatible = "fixed-layout";
	#address-cells = <1>;
	#size-cells = <1>;

	siul20_midr0 at 4009c004 {
	  reg = <0x4009c004 0x4>;
	};

	siul20_midr1 at 4009c008 {
	  reg = <0x4009c008 0x4>;
	};

	siul21_midr0 at 44010004 {
	  reg = <0x44010004 0x4>;
	};

	siul21_midr1 at 44010008 {
	  reg = <0x44010008 0x4>;
	};
  };
};


[0]
https://lore.kernel.org/all/20250710142038.1986052-2-andrei.stefanescu@oss.nxp.com/
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/nvmem/nvmem.yaml#n82

-- 
Regards,
Ghennadi