[PATCH v5 8/8] ARM: dts: aspeed: yosemite5: Fix host0-ready and add POST end GPIO

[Kevin Tung]

Rename the unused PWRGD_CPU_PWROK_2 line to host0-ready and move the
previous host0-ready GPIO to FM_BIOS_POST_CMPLT_N.

The "host0-ready" line name is used by OpenBMC phosphor-state-manager
to determine whether the host firmware is running. The previous DTS
incorrectly mapped host0-ready to the POST end signal, causing
incorrect host firmware detection.

Map host0-ready to the correct power-good signal and use
FM_BIOS_POST_CMPLT_N as the POST end indicator.

Signed-off-by: Kevin Tung <kevin.tung.openbmc at gmail.com>
---
 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts
index f590ec6e00c48afe4ade1fb98011780ac0570e7c..beb971eadbe53b5d9fa49252a41bf7484a8e32da 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite5.dts
@@ -929,8 +929,8 @@ &sgpiom0 {
 	/*bit0-bit7*/
 	"PWRGD_CPU_PWROK","SGPIO_RSTBTN_OUT",
 	"PWRGD_CPU_PWROK_1","SGPIO_BMC_READY",
-	"PWRGD_CPU_PWROK_2","IBB_BMC_SRST",
-	"host0-ready","FM_I3C_SPD_AH_SEL_R",
+	"host0-ready","IBB_BMC_SRST",
+	"FM_BIOS_POST_CMPLT_N","FM_I3C_SPD_AH_SEL_R",
 	"PCIe_HP_BOOT","FM_I3C_SPD_IP_SEL_R",
 	"PCIe_HP_DATA","FM_JTAG_BMC_MUX_S0_R",
 	"PCIe_HP_NIC","FM_JTAG_BMC_MUX_S1_R",

-- 
2.53.0