[PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework

[Manikanta Maddireddy]

On 18/02/26 3:08 am, Niklas Cassel wrote:

> On Tue, Feb 17, 2026 at 11:24:40AM +0530, Manikanta Maddireddy wrote:
>> When Tegra194 runs in PCIe endpoint mode, BAR1–BAR5 are marked BAR_RESERVED so the
>> EPF does not allocate backing memory. The host-side pci_endpoint_test driver
>> still ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to
>> BAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks
>> CONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only
>> BAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no
>> longer available for real use (e.g. host DMA via BAR4).
>>
>> This series addresses that by:
>>
>> 1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core.
>>     BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may
>>     leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is
>>     for unused BARs that the EPC must disable in .init() and the EPF must not
>>     use. pci_epc_get_next_free_bar() treats both as not free.
>>
>> 2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4:
>>     BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA.
>>     Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay
>>     enabled so the host can use MSI-X and DMA.
>>
>> 3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the
>>     destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5
>>     (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B)
>>     to the pci_endpoint_test_tbl so the host driver can bind and run tests
>>     without corrupting MSI-X or DMA registers.
>>
>> 4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint
>>     (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of
>>     64-bit BAR0 and BAR2.
>>
>> With this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit
>> BAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use.
>>
> Hello Manikanta,
>
> There are quite a few things that I think we should implement differently,
> please see:
> https://lore.kernel.org/linux-pci/20260217212707.2450423-11-cassel@kernel.org/T/#u
>
> I'm not trying to take credit from you, for all I care, feel free to take
> over the series and add you Co-developed-by on all the patches.
>
> I just though that it would be easier to explain with code rather than a
> lot of back and forth.
>
> Hopefully we can send a V2 that includes more detailed BAR_RESERVED
> descriptions, that includes what are behind each BAR_RESERVED (including
> sizes of each backing MSI-X table/ATU regs/eDMA regs/whatever) in
> pcie-tegra194.c.
>
> I also have a Nvidia Jetson Orin Nano board that I can run in EP mode,
> so hopefully we can collaborate to get something merged for v7.1.
>
>
> Kind regards,
> Niklas

Hi Niklas,


I marked my series "Handled Elsewhere".
I sent new series to define HW reserved BARs.
https://lore.kernel.org/linux-pci/20260222193456.2460963-1-mmaddireddy@nvidia.com/T/#t

Thanks,
Manikanta