[PATCH v5 05/18] clk: mediatek: Add MT8189 vlpckgen clock support

[David Lechner]

On 2/2/26 12:28 AM, irving.ch.lin wrote:
> From: Irving-CH Lin <irving-ch.lin at mediatek.com>
> 
> Add support for the MT8189 vlpckgen clock controller, which provides
> muxes and dividers for clock selection in vlp domain for other IP blocks.
> 
> Signed-off-by: Irving-CH Lin <irving-ch.lin at mediatek.com>
> ---


> +static const char * const vlp_aud_adc_parents[] = {
> +	"clk26m",
> +	"vowpll",
> +	"aud_adc_ext",

I could not find a matching clock name for "aud_adc_ext" in any
of the other clock drivers. Which clock is this (i.e. what is the
macro name in mediatek,mt8189-clk.h)?

> +	"osc_d10"
> +};
> +