[PATCH] perf: arm_spe: Add barrier before enabling profiling buffer

[Will Deacon]

On Thu, Feb 19, 2026 at 12:08:27PM +0000, James Clark wrote:
> I'm back to drag this up again. So I think all of the above discussion
> relies on the ordering given by the indirect read needed for the "might
> ignore a direct write..." part. But it's _might_ ignore a direct write, it's
> possible for an implementation to not do that, so there are two possible
> implementations:
> 
> #1 Where there is an indirect read to give the write ignore outcome
> #2 Where there is no write ignore outcome so it doesn't require an
>    indirect read
> 
> For #2 there's nothing to force the ordering. We're writing to two different
> registers (PMBPTR_EL1 and PMBLIMITR_EL1) and we have to have the
> PMBLIMITR_EL1 write come second for the buffer to be considered configured
> correctly. For example if the old value of PMBPTR_EL1 is higher than the new
> PMBLIMITR_EL1 and the write to PMBLIMITR_EL1 happens first then it's
> misconfigured. That's why we think we need the isb() here.

I thought profiling was disabled in these cases, so why is it
misconfigured?

If it is misconfigured, what can go wrong given that we're either stopped
or pmscr is clear?

Will