[PATCH] mmc: sdhci-brcmstb: use correct register offset for V1 pin_sel restore

[Ulf Hansson]

On Mon, 16 Feb 2026 at 20:15, Kamal Dasu <kamal.dasu at broadcom.com> wrote:
>
> The restore path for SDIO_CFG_CORE_V1 was incorrectly using
> SDIO_CFG_SD_PIN_SEL (offset 0x44) instead of SDIO_CFG_V1_SD_PIN_SEL
> (offset 0x54), causing the wrong register to be written on resume.
> The save path already uses the correct V1-specific offset. This
> affects BCM7445 and BCM72116 platforms which use the V1 config core.
>
> Fixes: b7e614802e3f ("mmc: sdhci-brcmstb: save and restore registers during PM")
> Signed-off-by: Kamal Dasu <kamal.dasu at broadcom.com>

Applied for fixes and by adding a stable tag, thanks!

Kind regards
Uffe

> ---
>  drivers/mmc/host/sdhci-brcmstb.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
> index c9442499876c..57e45951644e 100644
> --- a/drivers/mmc/host/sdhci-brcmstb.c
> +++ b/drivers/mmc/host/sdhci-brcmstb.c
> @@ -116,7 +116,7 @@ static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core_ver v
>                 writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
>
>         if (ver == SDIO_CFG_CORE_V1) {
> -               writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
> +               writel(sr->sd_pin_sel, cr + SDIO_CFG_V1_SD_PIN_SEL);
>                 return;
>         }
>
> --
> 2.34.1
>