[PATCH 2/4] PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode

[Manikanta Maddireddy]

Tegra194 endpoint exposes three 64-bit BARs at indices 0, 2, and 4:
- BAR0+BAR1: EPF test/data (first 64-bit BAR)
- BAR2+BAR3: MSI-X table (HW-backed)
- BAR4+BAR5: DMA registers (HW-backed)

Update tegra_pcie_epc_features so that BAR0 is BAR_FIXED with only_64bit,
BAR1 is BAR_RESERVED (high half of 64-bit BAR0), BAR2/BAR3 are
BAR_RESERVED with only_64bit on BAR2 (MSI-X), and BAR4/BAR5 are
BAR_RESERVED with only_64bit on BAR4 (DMA).

In tegra_pcie_ep_init(), reset only BAR0 and BAR1 so that the first
64-bit BAR is disabled until the EPF enables it via set_bar. Do not
reset BAR2+BAR3 or BAR4+BAR5 so that MSI-X and DMA remain enabled for
the host.

This keeps CONSECUTIVE_BAR_TEST and DMA tests working while allowing
the host to use 64-bit BAR 2 (MSI-X) and 64-bit BAR 4 (DMA) for real
use.

BAR0 is capabale of supporting various sizes using DBI2 BAR registers
which are programmed in dw_pcie_ep_set_bar_programmable(), remove
1 MB size limit from pci_epc_features.

Signed-off-by: Manikanta Maddireddy <mmaddireddy at nvidia.com>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 1b4fc6a9bed1..6734d1336ef1 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1948,11 +1948,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
 static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
 
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-};
+	/*
+	 * Only reset the first 64-bit BAR (BAR0+BAR1); EPF will enable it via set_bar.
+	 * BAR2+BAR3 (MSI-X table) and BAR4+BAR5 (DMA regs) are HW-backed and must
+	 * stay enabled.
+	 */
+	dw_pcie_ep_reset_bar(pci, BAR_0);
+	dw_pcie_ep_reset_bar(pci, BAR_1);
+}
 
 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
 {
@@ -2009,16 +2013,16 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+/* Tegra194 EP: BAR0 = programmable BAR, BAR2 = MSI-X table, BAR4 = DMA regs. */
 static const struct pci_epc_features tegra_pcie_epc_features = {
 	.linkup_notifier = true,
 	.msi_capable = true,
-	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
-			.only_64bit = true, },
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
-	.bar[BAR_2] = { .type = BAR_RESERVED, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
-	.bar[BAR_4] = { .type = BAR_RESERVED, },
-	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },
+	.bar[BAR_1] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR0 */
+	.bar[BAR_2] = { .type = BAR_RESERVED, .only_64bit = true, },	/* MSI-X table */
+	.bar[BAR_3] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR2 */
+	.bar[BAR_4] = { .type = BAR_RESERVED, .only_64bit = true, },	/* DMA regs */
+	.bar[BAR_5] = { .type = BAR_RESERVED, },	/* high half of 64-bit BAR4 */
 	.align = SZ_64K,
 };
 

-- 
2.34.1