[PATCH net] net: sparx5/lan969x: fix DWRR cost max to match hardware register width

[Simon Horman]

On Tue, Feb 10, 2026 at 02:44:01PM +0100, Daniel Machon wrote:
> DWRR (Deficit Weighted Round Robin) scheduling distributes bandwidth
> across traffic classes based on per-queue cost values, where lower cost
> means higher bandwidth share.
> 
> The SPX5_DWRR_COST_MAX constant is 63 (6 bits) but the hardware
> register field HSCH_DWRR_ENTRY_DWRR_COST is GENMASK(24, 20), only
> 5 bits wide (max 31). This causes sparx5_weight_to_hw_cost() to
> compute cost values that silently overflow via FIELD_PREP, resulting
> in incorrect scheduling weights.
> 
> Set SPX5_DWRR_COST_MAX to 31 to match the hardware register width.
> 
> Fixes: 211225428d65 ("net: microchip: sparx5: add support for offloading ets qdisc")
> Signed-off-by: Daniel Machon <daniel.machon at microchip.com>

Reviewed-by: Simon Horman <horms at kernel.org>