[PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Move xlnx,irq-delay to common AXI DMA and MCDMA section

[Srinivas Neeli]

xlnx,irq-delay property is applicable to both AXI DMA and MCDMA
designs. Move it from "Optional properties for AXI DMA" to "Optional
properties for AXI DMA and MCDMA" section to correctly reflect its usage.

Signed-off-by: Srinivas Neeli <srinivas.neeli at amd.com>
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index b567107270cb..c9e75ce23d55 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -49,12 +49,12 @@ Optional properties for AXI DMA and MCDMA:
 	register as configured in h/w. Takes values {8...26}. If the property
 	is missing or invalid then the default value 23 is used. This is the
 	maximum value that is supported by all IP versions.
-
-Optional properties for AXI DMA:
-- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
 - xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
 	0-255. Setting this value to zero disables the delay timer interrupt.
 	1 timeout interval = 125 * clock period of SG clock.
+
+Optional properties for AXI DMA:
+- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1