[PATCH 1/4 v2] dt-bindings: serdes: s32g: Add NXP serdes subsystem
Vincent Guittot
vincent.guittot at linaro.org
Wed Feb 11 23:17:44 PST 2026
On Tue, 10 Feb 2026 at 01:40, Rob Herring <robh at kernel.org> wrote:
>
> On Tue, Feb 03, 2026 at 05:19:14PM +0100, Vincent Guittot wrote:
> > Describe the serdes subsystem available on the S32G platforms.
> >
> > Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>
> > ---
> > .../bindings/phy/nxp,s32g-serdes.yaml | 154 ++++++++++++++++++
> > 1 file changed, 154 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml b/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml
> > new file mode 100644
> > index 000000000000..fad34bee2a4f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml
> > @@ -0,0 +1,154 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/nxp,s32g-serdes.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NXP S32G2xxx/S32G3xxx SerDes PHY subsystem
> > +
> > +maintainers:
> > + - Ghennadi Procopciuc <ghennadi.procopciuc at nxp.com>
> > +
> > +description: |
> > + The SerDes subsystem on S32G SoC Family includes two types of PHYs:
> > + - One PCIe PHY: Supports various PCIe operation modes
> > + - Two Ethernet Physical Coding Sublayer (XPCS) controllers
> > +
> > + SerDes operation mode selects the enabled PHYs and speeds. Clock frequency
> > + must be adapted accordingly. Below table describes all possible operation
> > + modes.
> > +
> > + Mode PCIe XPCS0 XPCS1 PHY clock Description
> > + SGMII SGMII (MHz)
> > + -------------------------------------------------------------------------
> > + 0 Gen3 N/A N/A 100 Single PCIe
> > + 1 Gen2 1.25Gbps N/A 100 PCIe/SGMII
> > + 2 Gen2 N/A 1.25Gbps 100 PCIe/SGMII
> > + 3 N/A 1.25Gbps 1.25Gbps 100,125 SGMII
> > + 4 N/A 3.125/1.25Gbps 3.125/1.25Gbps 125 SGMII
> > + 5 Gen2 N/A 3.125Gbps 100 PCIe/SGMII
>
> Mixed tabs and spaces. Drop the tabs.
okay
>
> What's not clear to me is do you have 2 or 4 lanes?
2 lanes per serdes
as an example mode 0 is one PCIe x2 lane
and mode 1 is one PCIe x1 and one xpcs0/SGMII on lane 1
or mode 3 is one xpcs0/SGMII on lane 0 and one xpcs1/SGMII on lane 1
>
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - enum:
> > + - nxp,s32g2-serdes
> > + - items:
> > + - const: nxp,s32g3-serdes
> > + - const: nxp,s32g2-serdes
> > +
> > + reg:
> > + maxItems: 4
> > +
> > + reg-names:
> > + items:
> > + - const: ss_pcie
> > + - const: pcie_phy
> > + - const: xpcs0
> > + - const: xpcs1
> > +
> > + clocks:
> > + minItems: 4
> > + maxItems: 5
> > +
> > + clock-names:
> > + items:
> > + - const: axi
> > + - const: aux
> > + - const: apb
> > + - const: ref
> > + - const: ext
> > + minItems: 4
> > +
> > + resets:
> > + maxItems: 2
> > +
> > + reset-names:
> > + items:
> > + - const: serdes
> > + - const: pcie
> > +
> > + nxp,sys-mode:
> > + $ref: /schemas/types.yaml#/definitions/uint32
>
> maximum: 5
>
> Though isn't this redundant with the child nodes? You could use the
> standard 'phy-mode' property in each child.
not really because we can have mode 1 but only a node to describe
lane0 for PCIe x1 if the lane 1 is not used
>
> > + description: |
> > + SerDes operational mode. See above table for possible values.
> > +
> > + '#address-cells':
> > + const: 1
> > +
> > + '#size-cells':
> > + const: 0
> > +
> > +patternProperties:
> > + '^serdes[0,1]_lane@[0,1]$':
>
> Do you need to support serdes0_lane at 0 and serdes1_lane at 0 (or similar
> with "@1")? That's illegal as you have 2 nodes with the same address.
okay, we can find other naming
>
> > + description:
> > + Describe a serdes lane.
> > + type: object
> > +
> > + properties:
> > + compatible:
> > + enum:
> > + - nxp,s32g2-serdes-pcie-phy
> > + - nxp,s32g2-serdes-xpcs
>
> Seems like phy-mode would be sufficient. Are these separate blocks from
> the parent?
Isn't phy-mode only for ethernet phy ?
here we have either a PCIe phy or a xpcs instance which are referenced
with phandle
>
> > +
> > + reg:
> > + maxItems: 1
>
> Just 'maximum: 1' instead.
okay
>
> > +
> > + '#phy-cells':
> > + const: 0
> > +
> > + required:
> > + - reg
> > + - compatible
> > +
> > + unevaluatedProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - clocks
> > + - clock-names
> > + - resets
> > + - reset-names
> > + - nxp,sys-mode
> > + - '#address-cells'
> > + - '#size-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + bus {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + serdes0: serdes at 40480000 {
> > + compatible = "nxp,s32g3-serdes", "nxp,s32g2-serdes";
> > + reg = <0x0 0x40480000 0x0 0x108>,
> > + <0x0 0x40483008 0x0 0x10>,
> > + <0x0 0x40482000 0x0 0x800>,
> > + <0x0 0x40482800 0x0 0x800>;
> > + reg-names = "ss_pcie", "pcie_phy", "xpcs0", "xpcs1";
> > + clocks = <&clks 1>,
> > + <&clks 2>,
> > + <&clks 3>,
> > + <&clks 4>,
> > + <&serdes_100_ext>;
> > + clock-names = "axi", "aux", "apb", "ref", "ext";
> > + resets = <&reset 9>,
> > + <&reset 8>;
> > + reset-names = "serdes", "pcie";
> > + nxp,sys-mode = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + phy_pcie0: serdes0_lane at 0 {
> > + compatible = "nxp,s32g2-serdes-pcie-phy";
> > + #phy-cells = <0>;
> > + reg = <0>;
> > + };
> > + phy_xpcs0_0: serdes0_lane at 1 {
> > + compatible = "nxp,s32g2-serdes-xpcs";
> > + reg = <0>;
> > + };
> > + };
> > + };
> > --
> > 2.43.0
> >
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