[Linux-stm32] [PATCH v2 13/15] arm64: dts: st: add pinctrl nodes on stm32mp21

[Patrice CHOTARD]

On 11/18/25 17:19, Antonio Borneo wrote:
> Update the device-tree stm32mp211.dtsi to add the nodes for pinctrl.
> 
> Signed-off-by: Antonio Borneo <antonio.borneo at foss.st.com>
> ---
>  arch/arm64/boot/dts/st/stm32mp211.dtsi | 142 +++++++++++++++++++++++++
>  1 file changed, 142 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
> index 4bdf4b3a39829..fd561a85027c3 100644
> --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi
> @@ -3,6 +3,7 @@
>   * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
>   * Author: Alexandre Torgue <alexandre.torgue at foss.st.com> for STMicroelectronics.
>   */
> +#include <dt-bindings/clock/st,stm32mp21-rcc.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  
>  / {
> @@ -205,6 +206,124 @@ syscfg: syscon at 44230000 {
>  			reg = <0x44230000 0x0 0x10000>;
>  		};
>  
> +		pinctrl: pinctrl at 44240000 {
> +			bootph-all;

After a discussion with Alex, it's preferable to add bootph-* properties in board file instead of SoC files.
as done in this series :
https://lore.kernel.org/linux-arm-kernel/20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com/

Thanks
Patrice


> +			compatible = "st,stm32mp215-pinctrl";
> +			ranges = <0 0x44240000 0x80400>;
> +			interrupt-parent = <&exti1>;
> +			st,syscfg = <&exti1 0x60 0xff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			gpioa: gpio at 44240000 {
> +				bootph-all;
> +				reg = <0x0 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOA>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOA";
> +				status = "disabled";
> +			};
> +
> +			gpiob: gpio at 44250000 {
> +				bootph-all;
> +				reg = <0x10000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOB>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOB";
> +				status = "disabled";
> +			};
> +
> +			gpioc: gpio at 44260000 {
> +				bootph-all;
> +				reg = <0x20000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOC>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOC";
> +				status = "disabled";
> +			};
> +
> +			gpiod: gpio at 44270000 {
> +				bootph-all;
> +				reg = <0x30000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOD>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOD";
> +				status = "disabled";
> +			};
> +
> +			gpioe: gpio at 44280000 {
> +				bootph-all;
> +				reg = <0x40000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOE>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOE";
> +				status = "disabled";
> +			};
> +
> +			gpiof: gpio at 44290000 {
> +				bootph-all;
> +				reg = <0x50000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOF>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOF";
> +				status = "disabled";
> +			};
> +
> +			gpiog: gpio at 442a0000 {
> +				bootph-all;
> +				reg = <0x60000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOG>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOG";
> +				status = "disabled";
> +			};
> +
> +			gpioh: gpio at 442b0000 {
> +				bootph-all;
> +				reg = <0x70000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOH>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOH";
> +				status = "disabled";
> +			};
> +
> +			gpioi: gpio at 442c0000 {
> +				bootph-all;
> +				reg = <0x80000 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOI>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOI";
> +				status = "disabled";
> +			};
> +		};
> +
>  		exti2: interrupt-controller at 442d0000 {
>  			compatible = "st,stm32mp1-exti", "syscon";
>  			reg = <0x442d0000 0x0 0x400>;
> @@ -267,6 +386,29 @@ exti2: interrupt-controller at 442d0000 {
>  				<&intc GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		pinctrl_z: pinctrl at 46200000 {
> +			bootph-all;
> +			compatible = "st,stm32mp215-z-pinctrl";
> +			ranges = <0 0x46200000 0x400>;
> +			interrupt-parent = <&exti1>;
> +			st,syscfg = <&exti1 0x60 0xff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			gpioz: gpio at 46200000 {
> +				bootph-all;
> +				reg = <0 0x400>;
> +				clocks = <&scmi_clk CK_SCMI_GPIOZ>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				st,bank-name = "GPIOZ";
> +				st,bank-ioport = <11>;
> +				status = "disabled";
> +			};
> +		};
> +
>  		intc: interrupt-controller at 4ac10000 {
>  			compatible = "arm,gic-400";
>  			reg = <0x4ac10000 0x0 0x1000>,