[PATCH 2/8] phy: zynqmp: Refactor bus width configuration into helper

[Pandey, Radhey Shyam]

[Public]

> -----Original Message-----
> From: Sean Anderson <sean.anderson at linux.dev>
> Sent: Tuesday, February 3, 2026 5:51 AM
> To: Laurent Pinchart <laurent.pinchart at ideasonboard.com>; Vinod Koul
> <vkoul at kernel.org>; linux-phy at lists.infradead.org
> Cc: Krzysztof Wilczyński <kwilczynski at kernel.org>; Lorenzo Pieralisi
> <lpieralisi at kernel.org>; Pandey, Radhey Shyam
> <radhey.shyam.pandey at amd.com>; linux-kernel at vger.kernel.org; Simek, Michal
> <michal.simek at amd.com>; linux-arm-kernel at lists.infradead.org; linux-
> pci at vger.kernel.org; Neil Armstrong <neil.armstrong at linaro.org>; Rob Herring
> <robh at kernel.org>; Havalige, Thippeswamy <thippeswamy.havalige at amd.com>;
> Manivannan Sadhasivam <mani at kernel.org>; Bjorn Helgaas
> <bhelgaas at google.com>; Sean Anderson <sean.anderson at linux.dev>
> Subject: [PATCH 2/8] phy: zynqmp: Refactor bus width configuration into helper
>
> Split off the bus width configuration into a helper function for reuse.
>
> Signed-off-by: Sean Anderson <sean.anderson at linux.dev>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
Thanks!
> ---
>
>  drivers/phy/xilinx/phy-zynqmp.c | 20 ++++++++++++--------
>  1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqmp.c
> index fe6b4925d166..0d3c578d0f3f 100644
> --- a/drivers/phy/xilinx/phy-zynqmp.c
> +++ b/drivers/phy/xilinx/phy-zynqmp.c
> @@ -502,6 +502,17 @@ static void xpsgtr_lane_set_protocol(struct xpsgtr_phy
> *gtr_phy)
>       }
>  }
>
> +/* Set the bus width */
> +static void xpsgtr_phy_init_bus_width(struct xpsgtr_phy *gtr_phy, u32 width)
> +{
> +     struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
> +     u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
> +     u32 val = width << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
> +
> +     xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
> +     xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
> +}
> +
>  /* Bypass (de)scrambler and 8b/10b decoder and encoder. */
>  static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
>  {
> @@ -535,14 +546,7 @@ static void xpsgtr_phy_init_sata(struct xpsgtr_phy
> *gtr_phy)
>  /* SGMII-specific initialization. */
>  static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
>  {
> -     struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
> -     u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
> -     u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy-
> >lane);
> -
> -     /* Set SGMII protocol TX and RX bus width to 10 bits. */
> -     xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
> -     xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
> -
> +     xpsgtr_phy_init_bus_width(gtr_phy, PROT_BUS_WIDTH_10);
>       xpsgtr_bypass_scrambler_8b10b(gtr_phy);
>  }
>
> --
> 2.35.1.1320.gc452695387.dirty