[PATCH v3 0/6] drm/sun4i: Support LVDS on D1s/T113 combo D-PHY

[Parthiban]

On 11/16/25 2:46 PM, Kuba Szczodrzyński wrote:
> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo
> MIPI DSI D-PHY" which is required when using single-link LVDS0. The same
> PD0..PD9 pins are used for either DSI or LVDS.
> 
> Other than having to use the combo D-PHY, LVDS output is configured in
> the same way as on older chips.
> 
> This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It
> is then configured by the LCD TCON, which allows connecting a
> single-link LVDS display panel.

Also one additional note is, current LVDS implementation in tcon doesn't
handle LVDS mode in "0x0084 LCD LVDS Configure". We have only bitwidth
handled. When using smaller LVDS panels vesa & jeida needs to be handled
separately. Not sure if the mode support bit is same across all the SoC's TCON,
but here is the diff which I have used to make it work for vesa-24 by tweaking
the a133 lvds hook.

commit 1f2d8983f78a11adab759160957a9cf6dc4296aa
Author: Parthiban Nallathambi <parthiban at linumiz.com>
Date:   Tue Feb 3 21:55:48 2026 +0530

    drm/sunxi: a133 add support for LVDS mode handling
    
    A133 supports both NS and JEIDA mode. Add support depends on the
    mode selected from the devicetree data mapping.
    
    Signed-off-by: Parthiban Nallathambi <parthiban at linumiz.com>

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 3bacc897217f..98a2fb7ed015 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -175,8 +175,34 @@ static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
 static void sun20i_tcon_setup_lvds_dphy(struct sun4i_tcon *tcon,
                                        const struct drm_encoder *encoder)
 {
+       struct drm_connector *connector;
+       struct drm_display_info *info;
        union phy_configure_opts opts = { };
 
+       connector = sun4i_tcon_get_connector(encoder);
+       if (!connector)
+               return;
+
+       info = &connector->display_info;
+       if (info->num_bus_formats != 1)
+               return;
+
+       switch (info->bus_formats[0]) {
+       case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+       case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+       case MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA:
+               regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
+                                  SUN4I_TCON0_LVDS_IF_MODE,
+                                  SUN4I_TCON0_LVDS_IF_MODE);
+               break;
+       case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+       case MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG:
+               regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
+                                  SUN4I_TCON0_LVDS_IF_MODE,
+                                  0);
+               break;
+       }
+
        if (!tcon->quirks->has_combo_dphy || !tcon->dphy)
                return;
 
@@ -550,7 +576,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
        else
                reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
 
-       regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
+       regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
+                          SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 | SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK,
+                          reg);
 
        /* Setup the polarity of the various signals */
        if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 7e6a5f500d37..fa45b070def2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -101,11 +101,12 @@
 
 #define SUN4I_TCON0_LVDS_IF_REG                        0x84
 #define SUN4I_TCON0_LVDS_IF_EN                         BIT(31)
+#define SUN4I_TCON0_LVDS_IF_MODE                       BIT(27)
 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK              BIT(26)
 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS            (1 << 26)
 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS            (0 << 26)
 #define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK               BIT(20)
-#define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0              (1 << 20)
+#define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0              BIT(20)
 #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK               BIT(4)
 #define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL             (1 << 4)
 #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV                        (0 << 4)

Shall this be same for all the TCON?

--
Thanks,
Parthiban
https://linumiz.com
https://www.linkedin.com/company/linumiz