[PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets

[Sean Anderson]

On 2/4/26 03:32, Pandey, Radhey Shyam wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
> 
>> -----Original Message-----
>> From: Sean Anderson <sean.anderson at linux.dev>
>> Sent: Tuesday, February 3, 2026 5:51 AM
>> To: Laurent Pinchart <laurent.pinchart at ideasonboard.com>; Vinod Koul
>> <vkoul at kernel.org>; linux-phy at lists.infradead.org
>> Cc: Krzysztof Wilczyński <kwilczynski at kernel.org>; Lorenzo Pieralisi
>> <lpieralisi at kernel.org>; Pandey, Radhey Shyam
>> <radhey.shyam.pandey at amd.com>; linux-kernel at vger.kernel.org; Simek, Michal
>> <michal.simek at amd.com>; linux-arm-kernel at lists.infradead.org; linux-
>> pci at vger.kernel.org; Neil Armstrong <neil.armstrong at linaro.org>; Rob Herring
>> <robh at kernel.org>; Havalige, Thippeswamy <thippeswamy.havalige at amd.com>;
>> Manivannan Sadhasivam <mani at kernel.org>; Bjorn Helgaas
>> <bhelgaas at google.com>; Sean Anderson <sean.anderson at linux.dev>; Conor
>> Dooley <conor+dt at kernel.org>; Krzysztof Kozlowski <krzk+dt at kernel.org>;
>> devicetree at vger.kernel.org
>> Subject: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets
>>
>> Add resets so we can hold the bridge in reset while we perform phy calibration.
> 
> Seems like this should a required property?

It's optional as it does not exist in previous versions of the
devicetree. In the past I have received pushback against making these
sort of properties required.

If the resets don't exist we just don't assert them and assume the
bootloader has deasserted them.

--Sean

> Rest looks fine to me.
> 
>>
>> Signed-off-by: Sean Anderson <sean.anderson at linux.dev>
>> ---
>>
>>  .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml  | 17 +++++++++++++++++
>>  1 file changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> index 9de3c09efb6e..7efb3dd9955f 100644
>> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> @@ -69,6 +69,18 @@ properties:
>>    power-domains:
>>      maxItems: 1
>>
>> +  resets:
>> +    maxItems: 3
>> +
>> +  reset-names:
>> +    items:
>> +      - description: APB register block reset
>> +        const: cfg
>> +      - description: AXI-PCIe bridge reset
>> +        const: bridge
>> +      - description: PCIe MAC reset
>> +        const: ctrl
>> +
>>    iommus:
>>      maxItems: 1
>>
>> @@ -117,6 +129,7 @@ examples:
>>      #include <dt-bindings/interrupt-controller/irq.h>
>>      #include <dt-bindings/phy/phy.h>
>>      #include <dt-bindings/power/xlnx-zynqmp-power.h>
>> +    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
>>      soc {
>>          #address-cells = <2>;
>>          #size-cells = <2>;
>> @@ -146,6 +159,10 @@ examples:
>>              msi-parent = <&nwl_pcie>;
>>              phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
>>              power-domains = <&zynqmp_firmware PD_PCIE>;
>> +            resets = <&zynqmp_reset ZYNQMP_RESET_PCIE_CFG>,
>> +                     <&zynqmp_reset ZYNQMP_RESET_PCIE_BRIDGE>,
>> +                     <&zynqmp_reset ZYNQMP_RESET_PCIE_CTRL>;
>> +            reset-names = "cfg", "bridge", "ctrl";
>>              iommus = <&smmu 0x4d0>;
>>              pcie_intc: legacy-interrupt-controller {
>>                  interrupt-controller;
>> --
>> 2.35.1.1320.gc452695387.dirty
>