[PATCH 3/3] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

[Sherry Sun]

> On Wed, Feb 04, 2026 at 10:32:04AM +0800, Sherry Sun wrote:
> > Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.
> >
> > Signed-off-by: Sherry Sun <sherry.sun at nxp.com>
> > ---
> 
> If prevous patch just add label, reg_m2_wlan, you can squash to this one.

Thanks, will try this method.

Best Regards
Sherry

> 
> Frank
> >  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 59
> ++++++++++++++++++++
> >  1 file changed, 59 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index f86d6b428a47..0b45ff73a5a9 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -250,6 +250,13 @@ cpu {
> >  		};
> >  	};
> >
> > +	usdhc1_pwrseq: usdhc1_pwrseq {
> > +		compatible = "mmc-pwrseq-simple";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_usdhc1_pwrseq>;
> > +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> > +	};
> > +
> >  	reserved-memory {
> >  		#address-cells = <2>;
> >  		#size-cells = <2>;
> > @@ -863,6 +870,19 @@ &uart3 {
> >  	status = "okay";
> >  };
> >
> > +&usdhc1 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc1>;
> > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> > +	keep-power-in-suspend;
> > +	non-removable;
> > +	wakeup-source;
> > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > +	vmmc-supply = <&reg_m2_wlan>;
> > +	status = "okay";
> > +};
> > +
> >  &usdhc2 {
> >  	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
> >  	assigned-clock-rates = <400000000>;
> > @@ -1169,6 +1189,45 @@
> MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
> >  		>;
> >  	};
> >
> > +	pinctrl_usdhc1: usdhc1grp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
> > +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0
> 	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1
> 	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2
> 	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3
> 	0x1d0
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
> > +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0
> 	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1
> 	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2
> 	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3
> 	0x1d4
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
> > +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0
> 	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1
> 	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2
> 	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3
> 	0x1d6
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_pwrseq: usdhc1pwrseq {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140
> > +		>;
> > +	};
> > +
> >  	pinctrl_usdhc2: usdhc2grp {
> >  		fsl,pins = <
> >  			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
> > --
> > 2.37.1
> >