[PATCH net-next v8 2/2] net: stmmac: Add support for Allwinner A523 GMAC200

[Chen-Yu Tsai]

On Wed, Oct 1, 2025 at 8:20 AM Jakub Kicinski <kuba at kernel.org> wrote:
>
> On Mon, 29 Sep 2025 18:08:04 -0700 Jakub Kicinski wrote:
> > On Fri, 26 Sep 2025 03:15:59 +0800 Chen-Yu Tsai wrote:
> > > The Allwinner A523 SoC family has a second Ethernet controller, called
> > > the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
> > > numbering. This controller, according to BSP sources, is fully
> > > compatible with a slightly newer version of the Synopsys DWMAC core.
> > > The glue layer around the controller is the same as found around older
> > > DWMAC cores on Allwinner SoCs. The only slight difference is that since
> > > this is the second controller on the SoC, the register for the clock
> > > delay controls is at a different offset. Last, the integration includes
> > > a dedicated clock gate for the memory bus and the whole thing is put in
> > > a separately controllable power domain.
> >
> > Hi Andrew, does this look good ?
> >
> > thread: https://lore.kernel.org/20250925191600.3306595-3-wens@kernel.org
>
> Adding Heiner and Russell, in case Andrew is AFK.
>
> We need an ack from PHY maintainers, the patch seems to be setting
> delays regardless of the exact RMII mode. I don't know these things..

AFAIK the delays only apply to the RGMII signal path, i.e. they are no-op
for RMII. Also, the delays are unrelated to the 2ns delay required by RGMII.
These delays are more for tweaking minute signal length differences.

ChenYu