[PATCH 1/3] dmaengine: xilinx_dma: Fix channel idle state management in interrupt handler

[Pandey, Radhey Shyam]

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Suraj Gupta <suraj.gupta2 at amd.com>
> Sent: Wednesday, September 17, 2025 7:06 PM
> To: vkoul at kernel.org; Pandey, Radhey Shyam <radhey.shyam.pandey at amd.com>;
> Simek, Michal <michal.simek at amd.com>
> Cc: dmaengine at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org
> Subject: [PATCH 1/3] dmaengine: xilinx_dma: Fix channel idle state management in
> interrupt handler
>
> Only mark the channel as idle and start new transfers when the active list is actually
> empty, ensuring proper channel state management and avoiding spurious transfer
> attempts.

Nit - also explain the spurious transfer scenario so that fixes tag is justified.
>
> Signed-off-by: Suraj Gupta <suraj.gupta2 at amd.com>
> Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Direct Memory
> Access Engine")
> ---
>  drivers/dma/xilinx/xilinx_dma.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index
> a34d8f0ceed8..9f416eae33d0 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1914,8 +1914,10 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void
> *data)
>                     XILINX_DMA_DMASR_DLY_CNT_IRQ)) {
>               spin_lock(&chan->lock);
>               xilinx_dma_complete_descriptor(chan);
> -             chan->idle = true;
> -             chan->start_transfer(chan);
> +             if (list_empty(&chan->active_list)) {
> +                     chan->idle = true;
> +                     chan->start_transfer(chan);
> +             }
>               spin_unlock(&chan->lock);
>       }
>
> --
> 2.25.1