[PATCH v7 0/3] PCI: imx6: Add external reference clock mode support

[Hongxing Zhu]

> -----Original Message-----
> From: Manivannan Sadhasivam <mani at kernel.org>
> Sent: 2025年9月20日 15:39
> To: Hongxing Zhu <hongxing.zhu at nxp.com>
> Cc: Frank Li <frank.li at nxp.com>; l.stach at pengutronix.de; lpieralisi at kernel.org;
> kwilczynski at kernel.org; robh at kernel.org; krzk+dt at kernel.org;
> conor+dt at kernel.org; bhelgaas at google.com; shawnguo at kernel.org;
> s.hauer at pengutronix.de; kernel at pengutronix.de; festevam at gmail.com;
> linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> devicetree at vger.kernel.org; imx at lists.linux.dev; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH v7 0/3] PCI: imx6: Add external reference clock mode
> support
> 
> On Thu, Sep 18, 2025 at 11:25:52AM +0800, Richard Zhu wrote:
> > i.MX95 PCIes have two reference clock inputs: one from internal PLL,
> > the other from off chip crystal oscillator. The "extref" clock refers
> > to a reference clock from an external crystal oscillator.
> >
> > Add external reference clock input mode support for i.MX95 PCIes.
> >
> 
> Driver change looks good to me (except a nitpick that I reported, but I could fix
> it while applying), but the binding patches need to be reviewed by the DT
> binding maintainers.
Hi Mani:
Thanks a lot for your kindly help.

Hi Krzysztof:
Can you help to take a look at the first two dt-binding patches?
Sorry to send out this patch-set late, because that I mis-understood
 what's your means in the previous review around.

Best Regards
Richard Zhu
> 
> - Mani
> 
> > Main change in v7:
> > - Refine the subjects and commit message refer to Bjorn's comments.
> >
> > Main change in v6:
> > - Refer to Krzysztof's comments, let i.MX95 PCIes has the "ref" clock
> >   since it is wired actually, and add one more optional "extref" clock
> >   for i.MX95 PCIes.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250917045238.1048484-1-hongxing.zhu%40nxp.co
> m%2F
> >
> &data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008d
> df818c
> >
> 705%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63893950749741
> 1261%7C
> >
> Unknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlAi
> >
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=B
> Gjzm9
> > %2FClFXNW9cMNYXIps6LwwxBx%2FX%2BzX%2B1Njijw20%3D&reserved=0
> >
> > Main change in v5:
> > - Update the commit message of first patch refer to Bejorn's comments.
> > - Correct the typo error and update the description of property in the
> >   first patch.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250915035348.3252353-1-hongxing.zhu%40nxp.co
> m%2F
> >
> &data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008d
> df818c
> >
> 705%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63893950749743
> 6951%7C
> >
> Unknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlAi
> >
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=S
> NH5kT
> > uJ2Qj1WWRD%2FomjWS1nZOxSjcw1of%2FWG2LPayc%3D&reserved=0
> >
> > Main change in v4:
> > - Add one more reference clock "extref" to be onhalf the reference clock
> >   that comes from external crystal oscillator.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250626073804.3113757-1-hongxing.zhu%40nxp.co
> m%2F
> >
> &data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008d
> df818c
> >
> 705%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63893950749745
> 2416%7C
> >
> Unknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlAi
> >
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=8
> jduPW
> > G2eNaO2DH3yQfIP2JM%2F3GNcR3HeXJYD3FWX2I%3D&reserved=0
> >
> > Main change in v3:
> > - Update the logic check external reference clock mode is enabled or
> >   not in the driver codes.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250620031350.674442-1-hongxing.zhu%40nxp.com
> %2F&
> >
> data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008ddf
> 818c7
> >
> 05%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638939507497467
> 169%7CU
> >
> nknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwM
> CIsIlAiO
> >
> iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=iK
> wlgqy
> > k9mtl6n48E8mwPLXw1kWMtatc3j084TEqePM%3D&reserved=0
> >
> > Main change in v2:
> > - Fix yamllint warning.
> > - Refine the driver codes.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250619091004.338419-1-hongxing.zhu%40nxp.com
> %2F&
> >
> data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008ddf
> 818c7
> >
> 05%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638939507497482
> 698%7CU
> >
> nknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwM
> CIsIlAiO
> >
> iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=AS
> vy6X%
> > 2BYrzeyjoAvtGBxHu3lBwMXmSvIqdUEDSofIhc%3D&reserved=0
> >
> > [PATCH v7 1/3] dt-bindings: PCI: dwc: Add external reference clock
> > [PATCH v7 2/3] dt-bindings: PCI: pci-imx6: Add external reference
> > [PATCH v7 3/3] PCI: imx6: Add external reference clock input mode
> >
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml      |  3 +++
> > Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml |  6
> ++++++
> > drivers/pci/controller/dwc/pci-imx6.c                          | 20
> +++++++++++++-------
> > 3 files changed, 22 insertions(+), 7 deletions(-)
> >
> 
> --
> மணிவண்ணன் சதாசிவம்