[RESEND PATCH v5] arm64: Enable vmalloc-huge with ptdump

[Dev Jain]

On 17/09/25 9:13 pm, Will Deacon wrote:
> On Tue, Sep 16, 2025 at 11:30:26AM +0100, Will Deacon wrote:
>> I'm currently trying to put together a litmus test with James (cc'd) so
>> maybe we can help you out with that part.
> Here's what we came up with. There's not a good way to express the IPI
> from kick_all_cpus_sync() but it turns out that the ISB from the TLB
> invalidation is sufficient anyway. Does it make sense to you?
>
>
> AArch64 ptdump
> Variant=Ifetch
> {
> uint64_t pud=0xa110c;
> uint64_t pmd;
>
> 0:X0=label:"P1:L0"; 0:X1=instr:"NOP"; 0:X2=lock; 0:X3=pud; 0:X4=pmd;
>                      1:X1=0xdead;      1:X2=lock; 1:X3=pud; 1:X4=pmd;
> }
>   P0				| P1				;
>   (* static_key_enable *)	| (* pud_free_pmd_page *)	;
>   STR	W1, [X0]		| LDR	X9, [X3]		;
>   DC	CVAU,X0			| STR	XZR, [X3]		;
>   DSB	ISH			| DSB	ISH			;
>   IC	IVAU,X0			| ISB				;
>   DSB	ISH			|				;
>   ISB				| (* static key *)		;
> 				| L0:				;
>   (* mmap_lock *)		| B	out1			;
>   Lwlock:			|				;
>   MOV	W7, #1			| (* mmap_lock *)		;
>   SWPA	W7, W8, [X2]		| Lrlock:			;
> 				| MOV	W7, #1			;
> 				| SWPA	W7, W8, [X2]		;
>   (* walk pgtable *)		|				;
>   LDR	X9, [X3]		| (* mmap_unlock *)		;
>   CBZ	X9, out0		| STLR	WZR, [X2]		;
>   EOR	X10, X9, X9		|				;
>   LDR	X11, [X4, X10]		| out1:				;
> 				| EOR	X10, X9, X9		;
>   out0:				| STR	X1, [X4, X10]		;
>
> exists (0:X8=0 /\ 1:X8=0 /\	(* Lock acquisitions succeed *)
> 	0:X9=0xa110c /\		(* P0 sees the valid PUD ...*)
> 	0:X11=0xdead)		(* ... but the freed PMD *)
>
>
> Will

Is the syntax correct? I cannot use the herd7 command to run this.

Apart from that the test looks good to me.