[PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip

[Bough Chen]

> -----Original Message-----
> From: Peng Fan (OSS) <peng.fan at oss.nxp.com>
> Sent: 2025年9月19日 17:31
> To: Michael Walle <michael at walle.cc>
> Cc: Bough Chen <haibo.chen at nxp.com>; Rob Herring <robh at kernel.org>;
> Krzysztof Kozlowski <krzk+dt at kernel.org>; Conor Dooley
> <conor+dt at kernel.org>; Shawn Guo <shawnguo at kernel.org>; Sascha Hauer
> <s.hauer at pengutronix.de>; Pengutronix Kernel Team
> <kernel at pengutronix.de>; Fabio Estevam <festevam at gmail.com>; Peng Fan
> <peng.fan at nxp.com>; Frank Li <frank.li at nxp.com>; Marco Felsch
> <m.felsch at pengutronix.de>; Han Xu <han.xu at nxp.com>;
> devicetree at vger.kernel.org; imx at lists.linux.dev;
> linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of
> spi nor chip
> 
> On Fri, Sep 19, 2025 at 09:29:41AM +0200, Michael Walle wrote:
> >Hi,
> >
> >On Thu Sep 18, 2025 at 11:01 AM CEST, Peng Fan wrote:
> >> On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
> >> >The spi nor on imx8mm evk board works under SDR mode, and driver use
> >> >FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
> >> >According to the datasheet, there is IO limitation on this chip, the
> >> >max frequency of such case is 66MHz, so add the limitation here to
> >> >align with datasheet.
> >> >
> >> >Refer to 3.9.10 FlexSPI timing parameters on page 59.
> >> >https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
> >>
> >> The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports
> >> 33MHz and 66MHz. Saying the driver now only use RXCLKSRC 0 to
> >> restrict the device tree to 66MHz is not that correct.
> >>
> >> The SoC max frequency could be coded in driver per my understanding.
> >
> >Yes that is correct. The spi-max-frequency property is for the device,
> >not the capabilities of the controller. I.e. the flash chip on the
> >board.

Okay, I will add the rate limitation in host driver.

> >
> >> For the QSPI-NOR chip, the spi-max-frequency should represent the NOR
> >> chip frequency. But that chip supports SDR/DDR, so a new property
> >> spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
> >> CHIP SDR mode frequency?
> >
> >Which chip is it? I'm not sure that this is required because the
> >supported modes might be in the SFDP data and we just support the
> >8d8d8d mode backed by the JEDEC standard.
> 
> MT25QU256ABA
> Clock frequency
> – 166 MHz (MAX) for all protocols in STR – 90 MHz (MAX) for all protocols in
> DTR
> 
> Current spi-max-frequency does not indicate it is STR or DDR.
> 
> If device tree has spi-max-frequency as 166MHz, but driver configures the
> working mode as DDR, there might be issues. I not look into details on SFDP or
> 8d8d8d8d, so my understandings might be wrong.

Micron MT35x has more complicate limitation:
• Clock frequency:
– 166 MHz (MAX) in SDR (166 MB/s) (1.8V)
– 200 MHz (MAX) in DDR (400 MB/s) with DQS (1.8V)
– 133 MHz (MAX) in SDR (133 MB/s) (3.0V)
– 133 MHz (MAX) in DDR (266MB/s) with DQS (3.0V)

Seems need add this rate limitation in spi-nor driver for different chips.

Regards
Haibo Chen
> 
> Thanks,
> Peng
> 
> >
> >-michael
> >
> >> So if spi-max-frequency is the maximum NOR chip SDR frequency, the
> >> driver should also be update dthat DDR mode is not supported as of now.
> >>
> >> Just my thoughts.
> >>
> >> Regards
> >> Peng.
> >
>