[PATCH] iommu/arm-smmu-qcom: Enable use of all SMR groups when running bare-metal

[Will Deacon]

On Wed, Sep 17, 2025 at 09:16:46PM +0200, Stephan Gerhold wrote:
> I realize it is weird to allow non-architectural features like this, but
> I haven't found any indication that the additional SMRs work any
> different from the standard ones. The SMMU spec seems to reserve space
> for up to 256 SMRs in the address space and the register bits, as if it
> was intended to be extended like this later. That's also why it works
> correctly without any changes in arm-smmu.c: the bit masks used there
> already allow up to 256 SMRs.
> 
> What do you think?

Although it's all pretty ugly, I think we really only have two choices:

  - Teach the core driver code about all this and use an rmr-like scheme
    to leave the upper SMRs in bypass

  - Hack it in the impl code as per your patch

The latter option is probably the most pragmatic (especially considering
the need to handle the virtualised case differently) but I'd like to see
what Robin thinks.

Will