[PATCH v2] arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2

[Quentin Schulz]

Hi Chaoyi Chen,

On 9/18/25 8:28 AM, Chaoyi Chen wrote:
> From: Chaoyi Chen <chaoyi.chen at rock-chips.com>
> 
> The rk3588 evb2 board has a full size DisplayPort connector, enable
> for it.
> 
> Signed-off-by: Chaoyi Chen <chaoyi.chen at rock-chips.com>
> ---
> 
> Changes in v2:
> 
> - Link to V1: https://lore.kernel.org/all/20250916080802.125-1-kernel@airkyi.com/
> - Fix invalid DP connector type
> - Add more comment about dclk_vp2 parent clock
> 
>   .../boot/dts/rockchip/rk3588-evb2-v10.dts     | 48 +++++++++++++++++++
>   1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> index 91fe810d38d8..60ba6ac55b23 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
> @@ -25,6 +25,18 @@ chosen {
>   		stdout-path = "serial2:1500000n8";
>   	};
>   
> +	dp-con {
> +		compatible = "dp-connector";
> +		label = "DP OUT";
> +		type = "full-size";
> +
> +		port {
> +			dp_con_in: endpoint {
> +				remote-endpoint = <&dp0_out_con>;
> +			};
> +		};
> +	};
> +
>   	hdmi-con {
>   		compatible = "hdmi-connector";
>   		type = "a";
> @@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
>   	};
>   };
>   
> +&dp0 {
> +	pinctrl-0 = <&dp0m0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&dp0_in {
> +	dp0_in_vp2: endpoint {
> +		remote-endpoint = <&vp2_out_dp0>;
> +	};
> +};
> +
> +&dp0_out {
> +	dp0_out_con: endpoint {
> +		remote-endpoint = <&dp_con_in>;
> +	};
> +};
> +
>   &gpu {
>   	mali-supply = <&vdd_gpu_s0>;
>   	sram-supply = <&vdd_gpu_mem_s0>;
> @@ -916,6 +946,17 @@ &usb_host1_xhci {
>   };
>   
>   &vop {
> +	/*
> +	 * If no dedicated PLL was specified, the GPLL would be automatically
> +	 * assigned as the PLL source for dclk_vop2. As the frequency of GPLL
> +	 * is 1188 MHz, we can only get typical clock frequencies such as
> +	 * 74.25MHz, 148.5MHz, 297MHz, 594MHz.
> +	 *
> +	 * So here we set the parent clock of VP2 to V0PLL so that we can get
> +	 * any frequency.
> +	 */
> +	assigned-clocks = <&cru DCLK_VOP2_SRC>;
> +	assigned-clock-parents = <&cru PLL_V0PLL>;

Are those board-specific? Considering the VOP and DP/HDMI/... 
controllers/PHYs are all internal to the SoC, would it make sense to 
have those specified in the SoC DTSI? I'm not familiar with the video 
output stack so maybe it doesn't apply here or is a bad idea, so I'm not 
actually asking for a change here, just asking a question :)

Cheers,
Quentin