[PATCH v5 6/7] arm64: dts: renesas: Add R8A78000 X5H DTs
Geert Uytterhoeven
geert at linux-m68k.org
Thu Sep 18 02:53:39 PDT 2025
Hi Morimoto-san,
On Thu, 18 Sept 2025 at 08:27, Kuninori Morimoto
<kuninori.morimoto.gx at renesas.com> wrote:
> From: Hai Pham <hai.pham.ud at renesas.com>
>
> Add initial DT support for R8A78000 (R-Car X5H) SoC.
>
> [Kuninori: tidyup for upstreaming]
>
> Signed-off-by: Hai Pham <hai.pham.ud at renesas.com>
> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz at renesas.com>
> Signed-off-by: Minh Le <minh.le.aj at renesas.com>
> Signed-off-by: Huy Bui <huy.bui.wm at renesas.com>
> Signed-off-by: Khanh Le <khanh.le.xr at renesas.com>
> Signed-off-by: Phong Hoang <phong.hoang.wz at renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> + extalr_clk: extalr-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* clock-frequency must be set on board */
> + };
> +
> + /*
> + * In the early phase, there is no clock control support,
> + * so assume that the clocks are enabled by default.
> + * Therefore, dummy clocks are used.
> + */
> + dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
Please keep nodes sorted (alphabetically, by node name).
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <266660000>;
> + };
> +
> + dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <66666000>;
> + };
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + prr: chipid at 189e0044 {
> + compatible = "renesas,prr";
> + reg = <0 0x189e0044 0 4>;
> + };
> +
> + /*
> + * The ARM GIC-720AE - View 1
> + *
> + * see
> + * r19uh0244ej0052-r-carx5h.pdf
> + * - attachments: 002_R-CarX5H_Address_Map_r0p51.xlsx
> + * - sheet [RT]
> + * - line 619
> + */
> + gic: interrupt-controller at 39000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0 0x39000000 0 0x20000>,
The DT bindings say the first region should be GICD (no mention of
GICM), so shouldn't the size be 0x10000?
See Table 21.9 "GIC-720AE Base address".
> + <0 0x39080000 0 0x800000>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + scif0: serial at c0700000 {
> + compatible = "renesas,scif-r8a78000", "renesas,rcar-gen5-scif", "renesas,scif";
Some lines are getting a bit long, but that is not something I cannot
fix while applying...
> + reg = <0 0xc0700000 0 0x40>;
> + interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + status = "disabled";
> + };
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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