[PATCH v3 5/6] arm64: dts: renesas: Add R8A78000 X5H DTs

Marc Zyngier maz at kernel.org
Wed Sep 17 00:53:27 PDT 2025


On Wed, 17 Sep 2025 05:08:21 +0100,
Kuninori Morimoto <kuninori.morimoto.gx at renesas.com> wrote:
> 
> 
> Hi Marc
> 
> > > +		/*
> > > +		 * The ARM GIC-720AE - View 1
> > > +		 *
> > > +		 * see
> > > +		 *	r19uh0244ej0052-r-carx5h.pdf
> > > +		 *	- attachments: 002_R-CarX5H_Address_Map_r0p51.xlsx
> > > +		 *	 - sheet [RT]
> > > +		 *	  - line 619
> > 
> > Are these documents publicly available? If not, I don't think this
> > helps much.
> 
> You can get it if you are Renesas R-Car Consortium member.

Given that statistically nobody outside of Renesas it a "member", the
relevance of this document is pretty much nil.

> And, the datasheet is very complex, I don't think people can find it by
> himself without any hint.

I guess we're just a bunch of inexperienced idiots unable to read a
TRM.

(eye roll...)

> 
> > > +		 */
> > > +		gic: interrupt-controller at 39000000 {
> > > +			compatible = "arm,gic-v3";
> > > +			#interrupt-cells = <3>;
> > > +			#address-cells = <0>;
> > > +			interrupt-controller;
> > > +			reg = <0 0x39000000 0 0x20000>, // GICD
> > > +			      <0 0x39080000 0 0x40000>; // GICR
> > 
> > In v2, you indicated that your GIC was configured for GICv4.1, which
> > implied 256kB frames for each redistributor. Here, you have either
> > just enough space for 32 RDs for a GICv3, or 16 RDs for GICv4.
> > 
> > So either this is wrong, and you're missing half of the RD space, or
> > v2 was wrong. Which one is it?
> 
> will fix in v4
> 
> > > +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > 
> > No ITS? That seems... surprising.
> 
> Will be added later

Why later? You're adding the GIC, add it all, not just a part of it.

	M.

-- 
Without deviation from the norm, progress is not possible.



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