[PATCH v3 3/6] arm64: cputype: Add Cortex-A720AE definitions

[Mark Rutland]

On Tue, Sep 16, 2025 at 09:53:00AM +0100, Will Deacon wrote:
> On Tue, Sep 16, 2025 at 02:38:36AM +0000, Kuninori Morimoto wrote:
> > Add cputype definitions for Cortex-A720AE.
> > This patch is assuming A720AE feature is same as A720.
> > 
> > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> > ---
> >  arch/arm64/include/asm/cputype.h       | 2 ++
> >  arch/arm64/kernel/cpu_errata.c         | 1 +
> >  arch/arm64/kernel/proton-pack.c        | 1 +
> >  tools/arch/arm64/include/asm/cputype.h | 2 ++
> >  tools/perf/util/arm-spe.c              | 1 +
> >  5 files changed, 7 insertions(+)
> > 
> > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> > index 661735616787e..b10eba7f52476 100644
> > --- a/arch/arm64/include/asm/cputype.h
> > +++ b/arch/arm64/include/asm/cputype.h
> > @@ -96,6 +96,7 @@
> >  #define ARM_CPU_PART_NEOVERSE_V3	0xD84
> >  #define ARM_CPU_PART_CORTEX_X925	0xD85
> >  #define ARM_CPU_PART_CORTEX_A725	0xD87
> > +#define ARM_CPU_PART_CORTEX_A720AE	0xD89

This MIDR is correct per Table A-187 in the Cortex-A720AE TRM, which can
be found at:

  https://developer.arm.com/documentation/102828/0001/

It would be nice to spell that out in the commit message, e.g. as in
commit:

  9ef54a384526 ("arm64: cputype: Add Cortex-A725 definitions")

> >  #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
> >  
> >  #define APM_CPU_PART_XGENE		0x000
> > @@ -185,6 +186,7 @@
> >  #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
> >  #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
> >  #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
> > +#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
> >  #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
> >  #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> >  #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> > index 59d723c9ab8f5..7ff6b49beaaff 100644
> > --- a/arch/arm64/kernel/cpu_errata.c
> > +++ b/arch/arm64/kernel/cpu_errata.c
> > @@ -531,6 +531,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = {
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
> > +	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
> > diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
> > index edf1783ffc817..f9a32dfde0067 100644
> > --- a/arch/arm64/kernel/proton-pack.c
> > +++ b/arch/arm64/kernel/proton-pack.c
> > @@ -884,6 +884,7 @@ static u8 spectre_bhb_loop_affected(void)
> >  	static const struct midr_range spectre_bhb_k38_list[] = {
> >  		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> >  		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> 
> This needs an Ack from somebody at Arm who can confirm that (a) k38 is
> correct for A720AE and (b) that all versions of the CPU are affected.

I can confirm both:

(a) The k value for Cortex-A720AE is 38.
(b) All versions of Cortex-A720AE are affected.

The Cortex-A720 and Cortex-A720AE cores are identical in this regard.

FWIW, that's described at:

  https://developer.arm.com/documentation/110280/3-0/?lang=en

... with the confusing caveat that the table describes this as 'No*",
meaning that it's only vulnerable to same-context attacks (which we DO
need to mitigate for BPF).

Listing Cortex-A720AE in the k38 table is the right thing to do. That'll
ensure the BPF mitigation is applied. Per the TRM linked above,
ID_AA64MMFR1_EL1.ECBHB==0b001, so we won't redundantly apply the
mitigation at exception entry.

> 
> > diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
> > index 139d5e87dc959..0192dc7ec9ca9 100644
> > --- a/tools/arch/arm64/include/asm/cputype.h
> > +++ b/tools/arch/arm64/include/asm/cputype.h
> > @@ -96,6 +96,7 @@
> >  #define ARM_CPU_PART_NEOVERSE_V3	0xD84
> >  #define ARM_CPU_PART_CORTEX_X925	0xD85
> >  #define ARM_CPU_PART_CORTEX_A725	0xD87
> > +#define ARM_CPU_PART_CORTEX_A720AE	0xD89
> >  #define ARM_CPU_PART_NEOVERSE_N3	0xD8E
> >  
> >  #define APM_CPU_PART_XGENE		0x000
> > @@ -185,6 +186,7 @@
> >  #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
> >  #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
> >  #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
> > +#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
> >  #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
> >  #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> >  #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> > diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
> > index 8942fa598a84f..bda6f3554f7e6 100644
> > --- a/tools/perf/util/arm-spe.c
> > +++ b/tools/perf/util/arm-spe.c
> > @@ -555,6 +555,7 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
> >  
> >  static const struct midr_range common_ds_encoding_cpus[] = {
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
> > +	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
> >  	MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
> 
> Please post tools/ patches separately as they are merged independently
> of the kernel changes.

Also, please add the ID definitions separately from any usage. That
makes them *much* easier to backport for handling errata, etc.

Mark.