[PATCH v2] arm64: versal-net: Describe L1/L2/L3/LLC caches
Michal Simek
michal.simek at amd.com
Fri Sep 12 04:02:16 PDT 2025
On 9/8/25 15:33, Michal Simek wrote:
> Add missing cache layout description.
>
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
>
> Changes in v2:
> - Also describe L1 caches
> - Add L1 to subject too
>
> v1:
> https://lore.kernel.org/r/f2ee23526349a0674149c969a2176c906e529402.1756825388.git.michal.simek@amd.com
>
>> lscpu --cache
> NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SIZE
> L1d 64K 1M 4 Data 1 256 64
> L1i 64K 1M 4 Instruction 1 256 64
> L2 512K 8M 8 Unified 2 1024 64
> L3 2M 8M 16 Unified 3 2048 64
> L4 16M 16M Unified 4
>
> ---
> arch/arm64/boot/dts/xilinx/versal-net.dtsi | 408 +++++++++++++++++++++
> 1 file changed, 408 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
> index c037a7819967..412af9a394aa 100644
> --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
> @@ -104,6 +104,28 @@ cpu0: cpu at 0 {
> reg = <0>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_00>;
> + l2_00: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> };
> cpu100: cpu at 100 {
> compatible = "arm,cortex-a78";
> @@ -112,6 +134,28 @@ cpu100: cpu at 100 {
> reg = <0x100>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_01>;
> + l2_01: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> };
> cpu200: cpu at 200 {
> compatible = "arm,cortex-a78";
> @@ -120,6 +164,28 @@ cpu200: cpu at 200 {
> reg = <0x200>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_02>;
> + l2_02: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> };
> cpu300: cpu at 300 {
> compatible = "arm,cortex-a78";
> @@ -128,6 +194,28 @@ cpu300: cpu at 300 {
> reg = <0x300>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_03>;
> + l2_03: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> };
> cpu10000: cpu at 10000 {
> compatible = "arm,cortex-a78";
> @@ -136,6 +224,28 @@ cpu10000: cpu at 10000 {
> reg = <0x10000>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_10>;
> + l2_10: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_1>;
> + };
> };
> cpu10100: cpu at 10100 {
> compatible = "arm,cortex-a78";
> @@ -144,6 +254,28 @@ cpu10100: cpu at 10100 {
> reg = <0x10100>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_11>;
> + l2_11: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_1>;
> + };
> };
> cpu10200: cpu at 10200 {
> compatible = "arm,cortex-a78";
> @@ -152,6 +284,28 @@ cpu10200: cpu at 10200 {
> reg = <0x10200>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_12>;
> + l2_12: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_1>;
> + };
> };
> cpu10300: cpu at 10300 {
> compatible = "arm,cortex-a78";
> @@ -160,6 +314,28 @@ cpu10300: cpu at 10300 {
> reg = <0x10300>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_13>;
> + l2_13: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_1>;
> + };
> };
> cpu20000: cpu at 20000 {
> compatible = "arm,cortex-a78";
> @@ -168,6 +344,28 @@ cpu20000: cpu at 20000 {
> reg = <0x20000>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_20>;
> + l2_20: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_2>;
> + };
> };
> cpu20100: cpu at 20100 {
> compatible = "arm,cortex-a78";
> @@ -176,6 +374,28 @@ cpu20100: cpu at 20100 {
> reg = <0x20100>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_21>;
> + l2_21: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_2>;
> + };
> };
> cpu20200: cpu at 20200 {
> compatible = "arm,cortex-a78";
> @@ -184,6 +404,28 @@ cpu20200: cpu at 20200 {
> reg = <0x20200>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_22>;
> + l2_22: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_2>;
> + };
> };
> cpu20300: cpu at 20300 {
> compatible = "arm,cortex-a78";
> @@ -192,6 +434,28 @@ cpu20300: cpu at 20300 {
> reg = <0x20300>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_23>;
> + l2_23: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_2>;
> + };
> };
> cpu30000: cpu at 30000 {
> compatible = "arm,cortex-a78";
> @@ -200,6 +464,28 @@ cpu30000: cpu at 30000 {
> reg = <0x30000>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_30>;
> + l2_30: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_3>;
> + };
> };
> cpu30100: cpu at 30100 {
> compatible = "arm,cortex-a78";
> @@ -208,6 +494,28 @@ cpu30100: cpu at 30100 {
> reg = <0x30100>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_31>;
> + l2_31: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_3>;
> + };
> };
> cpu30200: cpu at 30200 {
> compatible = "arm,cortex-a78";
> @@ -216,6 +524,28 @@ cpu30200: cpu at 30200 {
> reg = <0x30200>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_32>;
> + l2_32: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_3>;
> + };
> };
> cpu30300: cpu at 30300 {
> compatible = "arm,cortex-a78";
> @@ -224,7 +554,85 @@ cpu30300: cpu at 30300 {
> reg = <0x30300>;
> operating-points-v2 = <&cpu_opp_table>;
> cpu-idle-states = <&CPU_SLEEP_0>;
> + d-cache-size = <0x10000>; /* 64kB */
> + d-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + d-cache-sets = <256>;
> + i-cache-size = <0x10000>; /* 64kB */
> + i-cache-line-size = <64>;
> + /* 4 ways set associativity */
> + /* cache_size / (line_size / associativity) */
> + i-cache-sets = <256>;
> + next-level-cache = <&l2_33>;
> + l2_33: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x80000>; /* 512kB */
> + cache-line-size = <64>;
> + /* 8 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <1024>;
> + cache-unified;
> + next-level-cache = <&l3_3>;
> + };
> + };
> +
> + l3_0: l3-0-cache { /* cluster private */
> + compatible = "cache";
> + cache-level = <3>;
> + cache-size = <0x200000>; /* 2MB */
> + cache-line-size = <64>;
> + /* 16 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&llc>;
> + };
> +
> + l3_1: l3-1-cache { /* cluster private */
> + compatible = "cache";
> + cache-level = <3>;
> + cache-size = <0x200000>; /* 2MB */
> + cache-line-size = <64>;
> + /* 16 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&llc>;
> + };
> +
> + l3_2: l3-2-cache { /* cluster private */
> + compatible = "cache";
> + cache-level = <3>;
> + cache-size = <0x200000>; /* 2MB */
> + cache-line-size = <64>;
> + /* 16 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&llc>;
> + };
> +
> + l3_3: l3-3-cache { /* cluster private */
> + compatible = "cache";
> + cache-level = <3>;
> + cache-size = <0x200000>; /* 2MB */
> + cache-line-size = <64>;
> + /* 16 ways set associativity */
> + /* cache_size / (line_size/associativity) */
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&llc>;
> + };
> +
> + llc: l4-cache { /* LLC inside CMN */
> + compatible = "cache";
> + cache-level = <4>;
> + cache-size = <0x1000000>; /* 16MB */
> + cache-unified;
> };
> +
> idle-states {
> entry-method = "psci";
>
Applied.
M
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