[PATCH 13/33] arm_mpam: Add MPAM MSC register layout definitions
Shaopeng Tan (Fujitsu)
tan.shaopeng at fujitsu.com
Tue Sep 9 04:36:54 PDT 2025
Hello James,
> Memory Partitioning and Monitoring (MPAM) has memory mapped devices
> (MSCs) with an identity/configuration page.
>
> Add the definitions for these registers as offset within the page(s).
>
> Link: https://developer.arm.com/documentation/ihi0099/latest/
> Signed-off-by: James Morse <james.morse at arm.com>
> ---
> Changes since RFC:
> * Renamed MSMON_CFG_MBWU_CTL_TYPE_CSU as
> MSMON_CFG_CSU_CTL_TYPE_CSU
> * Whitepsace churn.
> * Cite a more recent document.
> * Removed some stale feature, fixed some names etc.
> ---
> drivers/resctrl/mpam_internal.h | 266
> ++++++++++++++++++++++++++++++++
> 1 file changed, 266 insertions(+)
>
> diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h
> index d49bb884b433..6e0982a1a9ac 100644
> --- a/drivers/resctrl/mpam_internal.h
> +++ b/drivers/resctrl/mpam_internal.h
> @@ -150,4 +150,270 @@ extern struct list_head mpam_classes; int
> mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
> cpumask_t *affinity);
>
> +/*
> + * MPAM MSCs have the following register layout. See:
> + * Arm Memory System Resource Partitioning and Monitoring (MPAM) System
> + * Component Specification.
> + * https://developer.arm.com/documentation/ihi0099/latest/
> + */
> +#define MPAM_ARCHITECTURE_V1 0x10
> +
> +/* Memory mapped control pages: */
> +/* ID Register offsets in the memory mapped page */
> +#define MPAMF_IDR 0x0000 /* features id register */
> +#define MPAMF_MSMON_IDR 0x0080 /* performance monitoring
> features */
> +#define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
> +#define MPAMF_CPOR_IDR 0x0030 /* cache-portion
> partitioning */
> +#define MPAMF_CCAP_IDR 0x0038 /* cache-capacity
> partitioning */
> +#define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
> +#define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
> +#define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */
> +#define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor
> */
> +#define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */
> +#define MPAMF_IIDR 0x0018 /* implementer id register */
> +#define MPAMF_AIDR 0x0020 /* architectural id register */
> +
> +/* Configuration and Status Register offsets in the memory mapped page */
> +#define MPAMCFG_PART_SEL 0x0100 /* partid to configure: */
> +#define MPAMCFG_CPBM 0x1000 /* cache-portion config */
> +#define MPAMCFG_CMAX 0x0108 /* cache-capacity config */
> +#define MPAMCFG_CMIN 0x0110 /* cache-capacity config */
> +#define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */
> +#define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw
> config */
> +#define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting
> window config */
> +#define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion
> bitmap config */
> +#define MPAMCFG_PRI 0x0400 /* priority partitioning
> config */
> +#define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */
> +#define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config
> */
> +
> +#define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */
> +#define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor
> filter */
> +#define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor
> config */
> +#define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */
> +#define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config
> */
> +#define MSMON_CSU 0x0840 /* current cache-usage */
> +#define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value
> captured */
> +#define MSMON_MBWU 0x0860 /* current mem-bw usage
> value */
> +#define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value
> captured */
> +#define MSMON_MBWU_L 0x0880 /* current long mem-bw
> usage value */
> +#define MSMON_MBWU_CAPTURE_L 0x0890 /* last long mem-bw value
> captured */
> +#define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */
> +#define MPAMF_ESR 0x00F8 /* error status register */
> +#define MPAMF_ECR 0x00F0 /* error control register */
> +
> +/* MPAMF_IDR - MPAM features ID register */
> +#define MPAMF_IDR_PARTID_MAX GENMASK(15, 0)
> +#define MPAMF_IDR_PMG_MAX GENMASK(23, 16)
> +#define MPAMF_IDR_HAS_CCAP_PART BIT(24)
> +#define MPAMF_IDR_HAS_CPOR_PART BIT(25)
> +#define MPAMF_IDR_HAS_MBW_PART BIT(26)
> +#define MPAMF_IDR_HAS_PRI_PART BIT(27)
> +#define MPAMF_IDR_EXT BIT(28)
> +#define MPAMF_IDR_HAS_IMPL_IDR BIT(29)
> +#define MPAMF_IDR_HAS_MSMON BIT(30)
> +#define MPAMF_IDR_HAS_PARTID_NRW BIT(31)
> +#define MPAMF_IDR_HAS_RIS BIT(32)
> +#define MPAMF_IDR_HAS_EXTD_ESR BIT(38)
> +#define MPAMF_IDR_HAS_ESR BIT(39)
> +#define MPAMF_IDR_RIS_MAX GENMASK(59, 56)
> +
> +/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
> +#define MPAMF_MSMON_IDR_MSMON_CSU BIT(16)
> +#define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17)
> +#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31)
> +
> +/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register
> */
> +#define MPAMF_CPOR_IDR_CPBM_WD
> GENMASK(15, 0)
> +
> +/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID
> register */
> +#define MPAMF_CCAP_IDR_CMAX_WD
> GENMASK(5, 0)
> +#define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8)
> +#define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28)
> +#define MPAMF_CCAP_IDR_HAS_CMIN BIT(29)
> +#define MPAMF_CCAP_IDR_NO_CMAX BIT(30)
> +#define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31)
> +
> +/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID
> register */
> +#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
> +#define MPAMF_MBW_IDR_HAS_MIN BIT(10)
> +#define MPAMF_MBW_IDR_HAS_MAX BIT(11)
> +#define MPAMF_MBW_IDR_HAS_PBM BIT(12)
> +#define MPAMF_MBW_IDR_HAS_PROP BIT(13)
> +#define MPAMF_MBW_IDR_WINDWR BIT(14)
> +#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)
> +
> +/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
> +#define MPAMF_PRI_IDR_HAS_INTPRI BIT(0)
> +#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1)
> +#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)
> +#define MPAMF_PRI_IDR_HAS_DSPRI BIT(16)
> +#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17)
> +#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)
> +
> +/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
> +#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)
> +#define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24)
> +#define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25)
> +#define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26)
> +#define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27)
> +#define MPAMF_CSUMON_IDR_HAS_XCL BIT(29)
> +#define MPAMF_CSUMON_IDR_CSU_RO BIT(30)
> +#define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31)
> +
> +/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID
> register */
> +#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)
> +#define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28)
> +#define MPAMF_MBWUMON_IDR_LWD BIT(29)
> +#define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30)
> +#define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31)
> +
> +/* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */
> +#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15,
> 0)
> +
> +/* MPAMF_IIDR - MPAM implementation ID register */
> +#define MPAMF_IIDR_PRODUCTID GENMASK(31, 20)
> +#define MPAMF_IIDR_PRODUCTID_SHIFT 20
> +#define MPAMF_IIDR_VARIANT GENMASK(19, 16)
> +#define MPAMF_IIDR_VARIANT_SHIFT 16
> +#define MPAMF_IIDR_REVISON GENMASK(15, 12)
> +#define MPAMF_IIDR_REVISON_SHIFT 12
> +#define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0)
> +#define MPAMF_IIDR_IMPLEMENTER_SHIFT 0
> +
> +/* MPAMF_AIDR - MPAM architecture ID register */
> +#define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4)
> +#define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0)
> +
> +/* MPAMCFG_PART_SEL - MPAM partition configuration selection register */
> +#define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0)
> +#define MPAMCFG_PART_SEL_INTERNAL BIT(16)
> +#define MPAMCFG_PART_SEL_RIS GENMASK(27, 24)
> +
> +/* MPAMCFG_CMAX - MPAM cache capacity configuration register */
> +#define MPAMCFG_CMAX_SOFTLIM BIT(31)
> +#define MPAMCFG_CMAX_CMAX GENMASK(15, 0)
> +
> +/* MPAMCFG_CMIN - MPAM cache capacity configuration register */
> +#define MPAMCFG_CMIN_CMIN GENMASK(15, 0)
> +
> +/*
> + * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning
> configuration
> + * register
> + */
> +#define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0)
> +
> +/*
> + * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning
> configuration
> + * register
> + */
> +#define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0)
> +#define MPAMCFG_MBW_MAX_HARDLIM BIT(31)
> +
> +/*
> + * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window
> width
> + * register
> + */
> +#define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0)
> +#define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8)
> +
> +/* MPAMCFG_PRI - MPAM priority partitioning configuration register */
> +#define MPAMCFG_PRI_INTPRI GENMASK(15, 0)
> +#define MPAMCFG_PRI_DSPRI GENMASK(31, 16)
> +
> +/*
> + * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride
> partitioning
> + * configuration register
> + */
> +#define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0)
> +#define MPAMCFG_MBW_PROP_EN BIT(31)
> +
> +/*
> + * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration
> +register */
> +#define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0)
> +#define MPAMCFG_INTPARTID_INTERNAL BIT(16)
> +
> +/* MSMON_CFG_MON_SEL - Memory system performance monitor selection
> register */
> +#define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0)
> +#define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24)
> +
> +/* MPAMF_ESR - MPAM Error Status Register */
> +#define MPAMF_ESR_PARTID_MON GENMASK(15, 0)
> +#define MPAMF_ESR_PMG GENMASK(23, 16)
> +#define MPAMF_ESR_ERRCODE GENMASK(27, 24)
> +#define MPAMF_ESR_OVRWR BIT(31)
> +#define MPAMF_ESR_RIS GENMASK(35, 32)
> +
> +/* MPAMF_ECR - MPAM Error Control Register */
> +#define MPAMF_ECR_INTEN BIT(0)
> +
> +/* Error conditions in accessing memory mapped registers */
> +#define MPAM_ERRCODE_NONE 0
> +#define MPAM_ERRCODE_PARTID_SEL_RANGE 1
> +#define MPAM_ERRCODE_REQ_PARTID_RANGE 2
> +#define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3
> +#define MPAM_ERRCODE_REQ_PMG_RANGE 4
> +#define MPAM_ERRCODE_MONITOR_RANGE 5
> +#define MPAM_ERRCODE_INTPARTID_RANGE 6
> +#define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7
> +
> +/*
> + * MSMON_CFG_CSU_FLT - Memory system performance monitor configure
> cache storage
> + * usage monitor filter register
> + */
> +#define MSMON_CFG_CSU_FLT_PARTID GENMASK(15, 0)
> +#define MSMON_CFG_CSU_FLT_PMG GENMASK(23, 16)
> +
> +/*
> + * MSMON_CFG_CSU_CTL - Memory system performance monitor configure
> cache storage
> + * usage monitor control register
> + * MSMON_CFG_MBWU_CTL - Memory system performance monitor
> configure memory
> + * bandwidth usage monitor control register
> + */
> +#define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0)
> +#define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15)
> +#define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16)
> +#define MSMON_CFG_x_CTL_MATCH_PMG BIT(17)
> +#define MSMON_CFG_x_CTL_SCLEN BIT(19)
> +#define MSMON_CFG_x_CTL_SUBTYPE
> GENMASK(22, 20)
> +#define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24)
> +#define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25)
> +#define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26)
> +#define MSMON_CFG_x_CTL_CAPT_RESET BIT(27)
> +#define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28)
> +#define MSMON_CFG_x_CTL_EN BIT(31)
> +
> +#define MSMON_CFG_MBWU_CTL_TYPE_MBWU
> 0x42
> +#define MSMON_CFG_CSU_CTL_TYPE_CSU 0
+#define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43?
Best regards,
Shaopeng TAN
> +/*
> + * MSMON_CFG_MBWU_FLT - Memory system performance monitor
> configure memory
> + * bandwidth usage monitor filter register
> + */
> +#define MSMON_CFG_MBWU_FLT_PARTID GENMASK(15, 0)
> +#define MSMON_CFG_MBWU_FLT_PMG
> GENMASK(23, 16)
> +#define MSMON_CFG_MBWU_FLT_RWBW
> GENMASK(31, 30)
> +
> +/*
> + * MSMON_CSU - Memory system performance monitor cache storage usage
> monitor
> + * register
> + * MSMON_CSU_CAPTURE - Memory system performance monitor cache
> storage usage
> + * capture register
> + * MSMON_MBWU - Memory system performance monitor memory
> bandwidth usage
> + * monitor register
> + * MSMON_MBWU_CAPTURE - Memory system performance monitor
> memory bandwidth usage
> + * capture register
> + */
> +#define MSMON___VALUE GENMASK(30, 0)
> +#define MSMON___NRDY BIT(31)
> +#define MSMON___NRDY_L BIT(63)
> +#define MSMON___L_VALUE GENMASK(43, 0)
> +#define MSMON___LWD_VALUE GENMASK(62, 0)
> +
> +/*
> + * MSMON_CAPT_EVNT - Memory system performance monitoring capture
> event
> + * generation register
> + */
> +#define MSMON_CAPT_EVNT_NOW BIT(0)
> +
> #endif /* MPAM_INTERNAL_H */
> --
> 2.20.1
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