[PATCH net-next v3 1/3] dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/T2H and RZ/N2H SoCs

[Krzysztof Kozlowski]

On Mon, Sep 08, 2025 at 11:58:59AM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Add device tree binding support for the Gigabit Ethernet MAC (GMAC) IP
> on Renesas RZ/T2H and RZ/N2H SoCs. While these SoCs use the same
> Synopsys DesignWare MAC version 5.20 as RZ/V2H, they are synthesized
> with different hardware configurations.
> 
> Add new compatible strings "renesas,r9a09g077-gbeth" for RZ/T2H and
> "renesas,r9a09g087-gbeth" for RZ/N2H, with the latter using RZ/T2H as
> fallback since they share identical GMAC IP.
> 
> Update the schema to handle hardware differences between SoC variants.
> RZ/T2H requires only 3 clocks compared to 7 on RZ/V2H, supports 8 RX/TX
> queue pairs instead of 4, and needs 2 reset controls with reset-names
> property versus a single unnamed reset. RZ/T2H also has the split header
> feature enabled which is disabled on RZ/V2H.
> 
> Add support for an optional pcs-handle property to connect the GMAC to
> the MIIC PCS converter on RZ/T2H. Use conditional schema validation to
> enforce the correct clock, reset, and interrupt configurations per SoC
> variant.
> 
> Extend the base snps,dwmac.yaml schema to accommodate the increased
> interrupt count, supporting up to 19 interrupts and extending the
> rx-queue and tx-queue interrupt name patterns to cover queues 0-7.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Best regards,
Krzysztof