[PATCH v3] arm64: dts: ti: k3-j721e-main: Add DSI and DPHY-TX

[Harikrishna Shenoy]

From: Rahul T R <r-ravikumar at ti.com>

TI's J721E SoC supports a DPI to DSI video signal conversion bridge on
it's platform bus. The IP is from Cadence, and it has a custom TI
wrapper around it to facilitate integration.

This IP takes the DPI video signals from DSS and alongwith the DPHY IP,
it transmits DSI video signals out of the SoC.

Add support for DSI bridge and the DPHY-TX.

Signed-off-by: Rahul T R <r-ravikumar at ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary at ti.com>
Signed-off-by: Harikrishna Shenoy <h-shenoy at ti.com>
---
Changelog v2 -> v3:
-Add dsi ports.
-Revert to phy lablels used in v1.

Link to v1- https://lore.kernel.org/all/20250822124622.1424473-1-h-shenoy@ti.com/
Link to v2- https://lore.kernel.org/all/20250904105915.3043773-1-h-shenoy@ti.com/
 
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index ab3666ff4297..78fde982aff0 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1887,6 +1887,45 @@ port at 4 {
 		};
 	};
 
+	dphy2: phy at 4480000 {
+		compatible = "ti,j721e-dphy";
+		reg = <0x00 0x04480000 0x00 0x1000>;
+		clocks = <&k3_clks 296 1>, <&k3_clks 296 3>;
+		clock-names = "psm", "pll_ref";
+		#phy-cells = <0>;
+		power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 296 3>;
+		assigned-clock-parents = <&k3_clks 296 4>;
+		assigned-clock-rates = <19200000>;
+		status = "disabled";
+	};
+
+	dsi0: dsi at 4800000 {
+		compatible = "ti,j721e-dsi";
+		reg = <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>;
+		clocks = <&k3_clks 150 1>, <&k3_clks 150 5>;
+		clock-names = "dsi_p_clk", "dsi_sys_clk";
+		power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&dphy2>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		dsi0_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port at 0 {
+				reg = <0>;
+			};
+
+			port at 1 {
+				reg = <1>;
+			};
+		};
+	};
+
 	dss: dss at 4a00000 {
 		compatible = "ti,j721e-dss";
 		reg =
-- 
2.34.1