[PATCH v8 1/2] dt-bindings: ethernet: eswin: Document for EIC7700 SoC
李志
lizhi2 at eswincomputing.com
Wed Oct 15 23:43:31 PDT 2025
Hi Bo Gan,
Please refer to the original email. Based on the v6 clock patchset
and v7 reset patchset you mentioned, we have provided an example
using macros.
Best regards,
Li Zhi
> -----原始邮件-----
> 发件人: "Bo Gan" <ganboing at gmail.com>
> 发送时间:2025-10-16 11:17:25 (星期四)
> 收件人: weishangjuan at eswincomputing.com, devicetree at vger.kernel.org, andrew+netdev at lunn.ch, davem at davemloft.net, edumazet at google.com, kuba at kernel.org, pabeni at redhat.com, mcoquelin.stm32 at gmail.com, alexandre.torgue at foss.st.com, rmk+kernel at armlinux.org.uk, yong.liang.choong at linux.intel.com, vladimir.oltean at nxp.com, prabhakar.mahadev-lad.rj at bp.renesas.com, jan.petrous at oss.nxp.com, inochiama at gmail.com, jszhang at kernel.org, 0x1207 at gmail.com, boon.khai.ng at altera.com, linux-kernel at vger.kernel.org, netdev at vger.kernel.org, linux-stm32 at st-md-mailman.stormreply.com, linux-arm-kernel at lists.infradead.org
> 抄送: ningyu at eswincomputing.com, linmin at eswincomputing.com, lizhi2 at eswincomputing.com, pinkesh.vaghela at einfochips.com, "Krzysztof Kozlowski" <krzysztof.kozlowski at linaro.org>, "Xuyang Dong" <dongxuyang at eswincomputing.com>
> 主题: Re: [PATCH v8 1/2] dt-bindings: ethernet: eswin: Document for EIC7700 SoC
>
> Hi Zhi, ShangJuan,
>
>
> On 10/15/25 04:40, weishangjuan at eswincomputing.com wrote:
> > From: Shangjuan Wei <weishangjuan at eswincomputing.com>
> >
> > Add ESWIN EIC7700 Ethernet controller, supporting clock
> > configuration, delay adjustment and speed adaptive functions.
> >
> > Signed-off-by: Zhi Li <lizhi2 at eswincomputing.com>
> > Signed-off-by: Shangjuan Wei <weishangjuan at eswincomputing.com>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> > ---
> > .../bindings/net/eswin,eic7700-eth.yaml | 127 ++++++++++++++++++
> > 1 file changed, 127 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> > new file mode 100644
> > index 000000000000..9ddbfe219ae2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> > @@ -0,0 +1,127 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Eswin EIC7700 SOC Eth Controller
> > +
> > +maintainers:
> > + - Shuang Liang <liangshuang at eswincomputing.com>
> > + - Zhi Li <lizhi2 at eswincomputing.com>
> > + - Shangjuan Wei <weishangjuan at eswincomputing.com>
> > +
> > +description:
> > + Platform glue layer implementation for STMMAC Ethernet driver.
> > +
> > +select:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - eswin,eic7700-qos-eth
> > + required:
> > + - compatible
> > +
> > +allOf:
> > + - $ref: snps,dwmac.yaml#
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: eswin,eic7700-qos-eth
> > + - const: snps,dwmac-5.20
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + interrupt-names:
> > + const: macirq
> > +
> > + clocks:
> > + items:
> > + - description: AXI clock
> > + - description: Configuration clock
> > + - description: GMAC main clock
> > + - description: Tx clock
> > +
> > + clock-names:
> > + items:
> > + - const: axi
> > + - const: cfg
> > + - const: stmmaceth
> > + - const: tx
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + reset-names:
> > + items:
> > + - const: stmmaceth
> > +
> > + rx-internal-delay-ps:
> > + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> > +
> > + tx-internal-delay-ps:
> > + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
> > +
> > + eswin,hsp-sp-csr:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + - description: Phandle to HSP(High-Speed Peripheral) device
> > + - description: Offset of phy control register for internal
> > + or external clock selection
> > + - description: Offset of AXI clock controller Low-Power request
> > + register
> > + - description: Offset of register controlling TX/RX clock delay
> > + description: |
> > + High-Speed Peripheral device needed to configure clock selection,
> > + clock low-power mode and clock delay.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - interrupt-names
> > + - phy-mode
> > + - resets
> > + - reset-names
> > + - rx-internal-delay-ps
> > + - tx-internal-delay-ps
> > + - eswin,hsp-sp-csr
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + ethernet at 50400000 {
> > + compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
> > + reg = <0x50400000 0x10000>;
> > + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
> > + <&d0_clock 193>;
>
> Can you let me know which clock I should use for EIC7700 (HiFive P550), if
> I apply this patchset on top of XuYang's v6 clock patchset? ref:
> https://lore.kernel.org/all/20251009092029.140-1-dongxuyang@eswincomputing.com/
> In your vendor kernel, you have EIC7700_CLK_HSP_ETH_[APP|CSR]_CLK, but in
> the v6 clock patchset, I couldn't find them. Please help translate
> <186> <171> <40> <193> to the macro of v6 clock patchset, so I can help
> test it.
>
> > + clock-names = "axi", "cfg", "stmmaceth", "tx";> + interrupt-parent = <&plic>;
> > + interrupts = <61>;
> > + interrupt-names = "macirq";
> > + phy-mode = "rgmii-id";
> > + phy-handle = <&phy0>;> + resets = <&reset 95>;
>
> For reset, I assume this <95> corresponds to EIC7700_RESET_HSP_ETH0_ARST,
> if applying on top of the v7 reset patchset, correct? ref:
> https://lore.kernel.org/all/20250930093132.2003-1-dongxuyang@eswincomputing.com/
>
> > + reset-names = "stmmaceth";
> > + rx-internal-delay-ps = <200>;
> > + tx-internal-delay-ps = <200>;
> > + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
> > + snps,axi-config = <&stmmac_axi_setup>;
> > + snps,aal;
> > + snps,fixed-burst;
> > + snps,tso;
> > + stmmac_axi_setup: stmmac-axi-config {
> > + snps,blen = <0 0 0 0 16 8 4>;
> > + snps,rd_osr_lmt = <2>;
> > + snps,wr_osr_lmt = <2>;
> > + };
> > + };
ethernet at 50400000 {
compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
reg = <0x50400000 0x10000>;
clocks = <&d0_clock EIC7700_CLK_GATE_HSP_ACLK>,
<&d0_clock EIC7700_CLK_GATE_HSP_CFG_CLK>,
<&d0_clock EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE>,
<&d0_clock EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK>;
clock-names = "axi", "cfg", "stmmaceth", "tx";
interrupt-parent = <&plic>;
interrupts = <61>;
interrupt-names = "macirq";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
resets = <&reset EIC7700_RESET_HSP_ETH0_ARST>;
reset-names = "stmmaceth";
rx-internal-delay-ps = <200>;
tx-internal-delay-ps = <200>;
eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
snps,axi-config = <&stmmac_axi_setup>;
snps,aal;
snps,fixed-burst;
snps,tso;
stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <2>;
snps,wr_osr_lmt = <2>;
};
};
> > --
> > 2.17.1
> >
>
> Bo
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