[PATCH v1 5/7] ARM: dts: rockchip: Add display subsystem for RK3368

[李维豪]

Hi

Sorry about that, I didn't notice this before, I will adjust it
according to the documentation.

Best regards,
WeiHao

Heiko Stübner <heiko at sntech.de> 于2025年8月31日周日 23:04写道：

>
> Hi,
>
> Am Sonntag, 31. August 2025, 12:48:53 Mitteleuropäische Sommerzeit schrieb WeiHao Li:
> > Add vop and display-subsystem nodes to RK3368's device tree.
> >
> > Signed-off-by: WeiHao Li <cn.liweihao at gmail.com>
>
> please use the appropriate patch prefix. For arm64 this should be
> arm64: dts: rockchip:
>
> The one you're using is from the arm32 side.
>
> Also please sort things appropriately both node-position and order of
> properties inside nodes, see
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst
>
>
> Heiko
>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3368.dtsi | 26 ++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > index 73618df7a..0e47bf59a 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> > @@ -858,6 +858,32 @@ vop_mmu: iommu at ff930300 {
> >               status = "disabled";
> >       };
> >
> > +     vop: vop at ff930000 {
> > +             compatible = "rockchip,rk3368-vop";
> > +             reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
> > +             reg-names = "regs", "gamma_lut";
> > +             interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> > +             clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
> > +             clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> > +             assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
> > +             assigned-clock-rates = <400000000>, <200000000>;
> > +             resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
> > +             reset-names = "axi", "ahb", "dclk";
> > +             iommus = <&vop_mmu>;
> > +             status = "disabled";
> > +
> > +             vop_out: port {
> > +                     #address-cells = <1>;
> > +                     #size-cells = <0>;
> > +             };
> > +     };
> > +
> > +     display_subsystem: display-subsystem {
> > +             compatible = "rockchip,display-subsystem";
> > +             ports = <&vop_out>;
> > +             status = "disabled";
> > +     };
> > +
> >       hevc_mmu: iommu at ff9a0440 {
> >               compatible = "rockchip,iommu";
> >               reg = <0x0 0xff9a0440 0x0 0x40>,
> >
>
>
>
>