[PATCH v3 2/6] drm/bridge: dw-hdmi-qp: Fixup timer base setup
Daniel Stone
daniel at fooishbar.org
Fri Aug 29 08:21:18 PDT 2025
Hi Cristian,
On Mon, 25 Aug 2025 at 10:57, Cristian Ciocaltea
<cristian.ciocaltea at collabora.com> wrote:
> @@ -1255,6 +1254,11 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
> return ERR_PTR(-ENODEV);
> }
>
> + if (!plat_data->ref_clk_rate) {
> + dev_err(dev, "Missing ref_clk rate\n");
> + return ERR_PTR(-ENODEV);
> + }
This introduces another bisect cliff, as the Rockchip integration
isn't added until patch 5/6, meaning together with the previous patch
the driver isn't usable between patches 1-5. It would be most sensible
I think to keep a default until the users have been fixed up. But
maybe a better sequence for this series would be:
* dev_err_probe() cleanup (easy, no dependencies)
* add refclk to plat_data (populated but unused)
* use refclk instead of hardcoded frequency in bridge driver, make it mandatory
* add CEC IRQ to plat_data (populated but unused)
* add CEC support to driver, probably make it not mandatory to provide
CEC IRQ in DT since it doesn't seem required for correct operation?
* enable CEC in defconfig
Cheers,
Daniel
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