[PATCH V2 1/4] dmaengine: Add support to configure and read IRQ coalescing parameters

[Vinod Koul]

On 23-07-25, 11:49, Gupta, Suraj wrote:
> > >  struct dma_slave_caps {
> > >       u32 src_addr_widths;
> > > @@ -520,6 +528,8 @@ struct dma_slave_caps {
> > >       bool cmd_terminate;
> > >       enum dma_residue_granularity residue_granularity;
> > >       bool descriptor_reuse;
> > > +     u32 coalesce_cnt;
> > > +     u32 coalesce_usecs;
> >
> > Why not selectively set interrupts for the descriptor. The dma descriptors are in order,
> > so one a descriptor is notified and complete, you can also complete the descriptors
> > before that. I would suggest to use that rather than define a new interface for this
> >
> 
> The reason I used struct dma_slave_config to pass coalesce and delay information to DMA driver is that the coalesce count is configured per channel in AXI DMA channel control register[1].
> AXI DMA IP doesn't have provision to set interrupt per descriptor[2].
> I can explore other ways to pass this information via struct dma_async_tx_descriptor or metadata, or any other way.
> Please let me know your thoughts.

dma_async_tx_descriptor has dma_ctrl_flags and one of them is
DMA_PREP_INTERRUPT which you can set for a descriptor and control when
you get the interrupt

I am not a fan of adding custom interfaces.

-- 
~Vinod