[PATCH v2 2/3] dt-bindings: clock: exynos990: Reorder IDs clocks and extend

[Denzeel Oliva]

> This looks like a massive ABI break, where is the justification for
> doing it?
>
> Cheers,
> Conor.

Hi Conor,

I reordered because the current IDs don’t match CMU_TOP:
the PLL mux select is in PLL_CON0, not CON3, which gave wrong/low rates.
I also added DPU/CMUREF and a missing fixed-factor path to stop bad rates
and clk_summary hangs on hardware.
I’d rather fix the mapping now than keep a wrong layout.

Thanks,
Denzeel