[PATCH v3 3/5] iommu: Add iommu_get_domain_for_dev_locked() helper
Jason Gunthorpe
jgg at nvidia.com
Thu Aug 21 06:14:26 PDT 2025
On Thu, Aug 21, 2025 at 08:11:05AM +0000, Tian, Kevin wrote:
> > From: Nicolin Chen <nicolinc at nvidia.com>
> > Sent: Tuesday, August 19, 2025 1:23 AM
> >
> > ... I found that in SMMUv3 driver, iommu_get_domain_for_dev() is
> > used to get the RID domain for an SVA domain:
> > arm_smmu_set_pasid()
> > arm_smmu_blocking_set_dev_pasid()
> >
> > These two are already given an "old" (SVA) domain pointer, FWIW.
> >
> > So, we may change to passing in the old domain as you suggested,
> > yet we still have to fix the iommu_get_domain_for_dev() in order
> > to reflect the RID domain correctly for the driver that calls it
> > (or even potentially) in some group->mutex locked context where
> > the RID domain might not be naturally passed in.
> >
>
> Out of curiosity.
>
> arm_smmu_blocking_set_dev_pasid()
>
> /*
> * When the last user of the CD table goes away downgrade the STE back
> * to a non-cd_table one.
> */
> if (!arm_smmu_ssids_in_use(&master->cd_table)) {
> struct iommu_domain *sid_domain =
> iommu_get_domain_for_dev(master->dev);
>
> if (sid_domain->type == IOMMU_DOMAIN_IDENTITY ||
> sid_domain->type == IOMMU_DOMAIN_BLOCKED)
> sid_domain->ops->attach_dev(sid_domain, dev);
> }
>
> why cannot downgrade apply to the case where the RID is attached to
> a DMA domain?
If the RID is a PAGING domain then it must be a S1 paging domain and there is
no downgrade possible.
It is impossible for the RID to be a S2 paging domain while ssids are
in use.
Jason
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