[PATCH v2 3/3] dt-bindings: phy: rockchip,pcie3-phy: add rockchip,phy-ref-use-pad

[Krzysztof Kozlowski]

On 07/08/2025 09:54, Krzysztof Kozlowski wrote:
> On Wed, Aug 06, 2025 at 03:38:23PM +0200, Rick Wertenbroek wrote:
>> >From the RK3588 Technical Reference Manual, Part1,
>> section 6.19 PCIe3PHY_GRF Register Description: "ref_use_pad"
>>
>> "Select reference clock connected to ref_pad_clk_p/ref_pad_clk_m.
>> Selects the external ref_pad_clk_p and ref_pad_clk_m inputs as the
>> reference clock source when asserted. When de-asserted, ref_alt_clk_p
>> and ref_alt_clk_m are the sources of the reference clock."
>>
>> The hardware reset value for this field is 0x1 (enabled).
>> Note that this register field is only available on RK3588, not on RK3568.
> 
> Then you miss restricting it (:false) in one of if:then: blocks.
> 
> Also, binding cannot be after the user. You need to reorder patches.
> 
> ...
> 
>>  
>> +  rockchip,phy-ref-use-pad:
>> +    description: which PHY should use the external pad as PCIe reference clock.
>> +      1 means use pad (default), 0 means use internal clock (PLL_PPLL).
> 
> Can't you deduce it from the presence of clock inputs? IOW, if the
> clocks are physically connected, is it even reasonable or possible to
> use internal clock?
> 
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    minItems: 2
>> +    maxItems: 2
>> +    items:
>> +      minimum: 0
>> +      maximum: 1
> 
> More precise:
> 
> items:
>   - description: PHY0 reference clock config
>   - description: PHY1 reference clock config
>   enum: [ 0, 1 ]

Eh, no, rather if this stays as int:

    items:
      - description: PHY0 reference clock config
        enum: [ 0, 1 ]
      - description: PHY1 reference clock config
        enum: [ 0, 1 ]
    default: [ 1, 1 ]


> default: [ 1, 1 ]
> 
> Anyway, default 1, 1 is pretty non-obvious, so this should be just
> non-unique-string-array (and property should be like
> rockchip,phy-ref-clk-source/sel).
> 
> 
> Best regards,
> Krzysztof
> 


Best regards,
Krzysztof