[PATCH] clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset

[Chen-Yu Tsai]

On Tue, 01 Oct 2024 11:50:16 +0100, Andre Przywara wrote:
> To work around a limitation in our clock modelling, we try to force two
> bits in the AUDIO0 PLL to 0, in the CCU probe routine.
> However the ~ operator only applies to the first expression, and does
> not cover the second bit, so we end up clearing only bit 1.
> 
> Group the bit-ORing with parentheses, to make it both clearer to read
> and actually correct.
> 
> [...]

Applied to clk-for-6.13 in git at github.com:linux-sunxi/linux-sunxi.git, thanks!

[1/1] clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
      commit: e0f253a52ccee3cf3eb987e99756e20c68a1aac9

Best regards,
-- 
Chen-Yu Tsai <wens at csie.org>