[PATCH v3 1/8] arm64/sysreg: Add definitions for immediate versions of MSR ALLINT

[Mark Rutland]

On Mon, Apr 15, 2024 at 06:47:51AM +0000, Liao Chang wrote:
> From: Mark Brown <broonie at kernel.org>
> 
> Encodings are provided for ALLINT which allow setting of ALLINT.ALLINT
> using an immediate rather than requiring that a register be loaded with
> the value to write. Since these don't currently fit within the scheme we
> have for sysreg generation add manual encodings like we currently do for
> other similar registers such as SVCR.
> 
> Since it is required that these immediate versions be encoded with xzr
> as the source register provide asm wrapper which ensure this is the
> case.
> 
> Signed-off-by: Mark Brown <broonie at kernel.org>
> Signed-off-by: Liao Chang <liaochang1 at huawei.com>
> ---
>  arch/arm64/include/asm/nmi.h    | 27 +++++++++++++++++++++++++++
>  arch/arm64/include/asm/sysreg.h |  2 ++
>  2 files changed, 29 insertions(+)
>  create mode 100644 arch/arm64/include/asm/nmi.h

We have helpers for manipulating PSTATE bits; AFAICT we only need the three
lines below:

----8<----
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e8999592f3af..5c209d07ae57e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -94,18 +94,21 @@
 
 #define PSTATE_PAN                     pstate_field(0, 4)
 #define PSTATE_UAO                     pstate_field(0, 3)
+#define PSTATE_ALLINT                  pstate_field(1, 0)
 #define PSTATE_SSBS                    pstate_field(3, 1)
 #define PSTATE_DIT                     pstate_field(3, 2)
 #define PSTATE_TCO                     pstate_field(3, 4)
 
 #define SET_PSTATE_PAN(x)              SET_PSTATE((x), PAN)
 #define SET_PSTATE_UAO(x)              SET_PSTATE((x), UAO)
+#define SET_PSTATE_ALLINT(x)           SET_PSTATE((x), ALLINT)
 #define SET_PSTATE_SSBS(x)             SET_PSTATE((x), SSBS)
 #define SET_PSTATE_DIT(x)              SET_PSTATE((x), DIT)
 #define SET_PSTATE_TCO(x)              SET_PSTATE((x), TCO)
 
 #define set_pstate_pan(x)              asm volatile(SET_PSTATE_PAN(x))
 #define set_pstate_uao(x)              asm volatile(SET_PSTATE_UAO(x))
+#define set_pstate_allint(x)           asm volatile(SET_PSTATE_ALLINT(x))
 #define set_pstate_ssbs(x)             asm volatile(SET_PSTATE_SSBS(x))
 #define set_pstate_dit(x)              asm volatile(SET_PSTATE_DIT(x))
---->8---- 

The addition of <asm/nmi.h> and refrences to <linux/cpumask.h> and
arm64_supports_nmi() don't seem like they should be part of this patch.

Mark.

> 
> diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h
> new file mode 100644
> index 000000000000..0c566c649485
> --- /dev/null
> +++ b/arch/arm64/include/asm/nmi.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2022 ARM Ltd.
> + */
> +#ifndef __ASM_NMI_H
> +#define __ASM_NMI_H
> +
> +#ifndef __ASSEMBLER__
> +
> +#include <linux/cpumask.h>
> +
> +extern bool arm64_supports_nmi(void);
> +
> +#endif /* !__ASSEMBLER__ */
> +
> +static __always_inline void _allint_clear(void)
> +{
> +	asm volatile(__msr_s(SYS_ALLINT_CLR, "xzr"));
> +}
> +
> +static __always_inline void _allint_set(void)
> +{
> +	asm volatile(__msr_s(SYS_ALLINT_SET, "xzr"));
> +}
> +
> +#endif
> +
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 9e8999592f3a..b105773c57ca 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -167,6 +167,8 @@
>   * System registers, organised loosely by encoding but grouped together
>   * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
>   */
> +#define SYS_ALLINT_CLR			sys_reg(0, 1, 4, 0, 0)
> +#define SYS_ALLINT_SET			sys_reg(0, 1, 4, 1, 0)
>  #define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
>  #define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
>  #define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
> -- 
> 2.34.1
>