[PATCH v2] ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board

[Alexandre TORGUE]

Hi Marek

On 6/28/24 02:57, Marek Vasut wrote:
> Add ethernet support for the DH STM32MP13xx DHCOR DHSBC carrier board.
> This carrier board is populated with two gigabit ethernet ports and two
> Realtek RTL8211F PHYs, both are described in this DT patch.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>

I already applied series which add the ETH support in mp13 DH board. Can 
you please resend a patch which only add the nvmem efuse stuff please ?

Alex



> ---
> Cc: Alexandre Torgue <alexandre.torgue at foss.st.com>
> Cc: Christophe Roullier <christophe.roullier at foss.st.com>
> Cc: Conor Dooley <conor+dt at kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
> Cc: Maxime Coquelin <mcoquelin.stm32 at gmail.com>
> Cc: Rob Herring <robh at kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: kernel at dh-electronics.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-stm32 at st-md-mailman.stormreply.com
> ---
> V2: Fold ARM: dts: stm32: Add phandle to nvmem efuse into STM32MP13xx ethernet
>      DT node into this patch and make the nvmem-cells/nvmem-cell-names specific
>      to this board
> ---
>   .../boot/dts/st/stm32mp135f-dhcor-dhsbc.dts   | 60 +++++++++++++++++++
>   1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> index 5f4f6b6e427a5..3cc9ad88d61bc 100644
> --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> @@ -22,6 +22,8 @@ / {
>   		     "st,stm32mp135";
>   
>   	aliases {
> +		ethernet0 = &ethernet1;
> +		ethernet1 = &ethernet2;
>   		serial2 = &usart1;
>   		serial3 = &usart2;
>   	};
> @@ -72,6 +74,64 @@ channel at 12 {
>   	};
>   };
>   
> +&ethernet1 {
> +	nvmem-cell-names = "mac-address";
> +	nvmem-cells = <&ethernet_mac1_address>;
> +	phy-handle = <&ethphy1>;
> +	phy-mode = "rgmii-id";
> +	pinctrl-0 = <&eth1_rgmii_pins_a>;
> +	pinctrl-1 = <&eth1_rgmii_sleep_pins_a>;
> +	pinctrl-names = "default", "sleep";
> +	st,ext-phyclk;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";
> +
> +		ethphy1: ethernet-phy at 1 {
> +			/* RTL8211F */
> +			compatible = "ethernet-phy-id001c.c916";
> +			interrupt-parent = <&gpiog>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
> +			reg = <1>;
> +			reset-assert-us = <15000>;
> +			reset-deassert-us = <55000>;
> +			reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +};
> +
> +&ethernet2 {
> +	nvmem-cell-names = "mac-address";
> +	nvmem-cells = <&ethernet_mac2_address>;
> +	phy-handle = <&ethphy2>;
> +	phy-mode = "rgmii-id";
> +	pinctrl-0 = <&eth2_rgmii_pins_a>;
> +	pinctrl-1 = <&eth2_rgmii_sleep_pins_a>;
> +	pinctrl-names = "default", "sleep";
> +	st,ext-phyclk;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";
> +
> +		ethphy2: ethernet-phy at 1 {
> +			/* RTL8211F */
> +			compatible = "ethernet-phy-id001c.c916";
> +			interrupt-parent = <&gpiog>;
> +			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
> +			reg = <1>;
> +			reset-assert-us = <15000>;
> +			reset-deassert-us = <55000>;
> +			reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +};
> +
>   &gpioa {
>   	gpio-line-names = "", "", "", "",
>   			  "", "DHSBC_USB_PWR_CC1", "", "",