[PATCH v2 08/13] arm64: dts: layerscape: rename node name "wdt" to "watchdog"
Frank Li
Frank.Li at nxp.com
Wed Jun 26 13:25:28 PDT 2024
Rename node name "wdt" to "watchdog" to fix below warning:
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dtb:
wdt at c000000: $nodename:0: 'wdt at c000000' does not match '^(timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$
Signed-off-by: Frank Li <Frank.Li at nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++--------
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 81b80b6b27d31..83236428e4cfd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -880,7 +880,7 @@ pcs7_3: ethernet-phy at 3 {
};
};
- cluster1_core0_watchdog: wdt at c000000 {
+ cluster1_core0_watchdog: watchdog at c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -890,7 +890,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core1_watchdog: wdt at c010000 {
+ cluster1_core1_watchdog: watchdog at c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -900,7 +900,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core2_watchdog: wdt at c020000 {
+ cluster1_core2_watchdog: watchdog at c020000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc020000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -910,7 +910,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core3_watchdog: wdt at c030000 {
+ cluster1_core3_watchdog: watchdog at c030000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc030000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -920,7 +920,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core0_watchdog: wdt at c100000 {
+ cluster2_core0_watchdog: watchdog at c100000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -930,7 +930,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core1_watchdog: wdt at c110000 {
+ cluster2_core1_watchdog: watchdog at c110000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -940,7 +940,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core2_watchdog: wdt at c120000 {
+ cluster2_core2_watchdog: watchdog at c120000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc120000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -950,7 +950,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core3_watchdog: wdt at c130000 {
+ cluster2_core3_watchdog: watchdog at c130000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc130000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index dac33a3eab841..fe4755c54af2e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -389,7 +389,7 @@ serial3: serial at 21d0600 {
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
};
- cluster1_core0_watchdog: wdt at c000000 {
+ cluster1_core0_watchdog: watchdog at c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -399,7 +399,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core1_watchdog: wdt at c010000 {
+ cluster1_core1_watchdog: watchdog at c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -409,7 +409,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core0_watchdog: wdt at c100000 {
+ cluster2_core0_watchdog: watchdog at c100000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -419,7 +419,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core1_watchdog: wdt at c110000 {
+ cluster2_core1_watchdog: watchdog at c110000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -429,7 +429,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster3_core0_watchdog: wdt at c200000 {
+ cluster3_core0_watchdog: watchdog at c200000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -439,7 +439,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster3_core1_watchdog: wdt at c210000 {
+ cluster3_core1_watchdog: watchdog at c210000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -449,7 +449,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster4_core0_watchdog: wdt at c300000 {
+ cluster4_core0_watchdog: watchdog at c300000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -459,7 +459,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster4_core1_watchdog: wdt at c310000 {
+ cluster4_core1_watchdog: watchdog at c310000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
--
2.34.1
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