[PATCH 0/5] arm64: errata: Expand speculative SSBS workaround

[Catalin Marinas]

On Mon, 03 Jun 2024 12:18:07 +0100, Mark Rutland wrote:
> A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS
> special-purpose register does not affect subsequent speculative
> instructions, permitting speculative store bypassing for a window of
> time.
> 
> We recently addressed this for Cortex-X4 and Neoverse-V3:
> 
> [...]

Applied to arm64 (for-next/errata), thanks!

[1/5] arm64: cputype: Add Cortex-X3 definitions
      https://git.kernel.org/arm64/c/be5a6f238700
[2/5] arm64: cputype: Add Cortex-A720 definitions
      https://git.kernel.org/arm64/c/add332c40328
[3/5] arm64: cputype: Add Cortex-X925 definitions
      https://git.kernel.org/arm64/c/fd2ff5f0b320
[4/5] arm64: errata: Unify speculative SSBS errata logic
      https://git.kernel.org/arm64/c/ec7687666080
[5/5] arm64: errata: Expand speculative SSBS workaround
      https://git.kernel.org/arm64/c/75b3c43eab59

-- 
Catalin