[PATCH 5/5] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()

[Peter Griffin]

Hi André,

On Tue, 7 May 2024 at 15:14, André Draszik <andre.draszik at linaro.org> wrote:
>
> While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk
> support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set
> on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
> the frequency of the reference clock for the USB2.0 phy instead.
>
> I stumbled across this while adding support for the Google Tensor
> gs101, but this should apply to E850 just the same.
>
> Do so.
>
> Fixes: 691525074db9 ("phy: exynos5-usbdrd: Add Exynos850 support")
> Signed-off-by: André Draszik <andre.draszik at linaro.org>
>
> ---
> Feel free to drop the Fixes: if you think that is unwarranted here.
>
> v2: add missing bitfield.h include (seems this is implied on some
>     platforms, but not on others)
> ---

Reviewed-by:  Peter Griffin <peter.griffin at linaro.org>

regards,

Peter

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