WARNING: drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c:364 vchiq_prepare_bulk_data

[Arnd Bergmann]

On Mon, Jun 10, 2024, at 10:26, Phil Elwell wrote:
> On Mon, 10 Jun 2024 at 07:00, Arnd Bergmann <arnd at arndb.de> wrote:
>
> Why is swiotlb involved at all? The DMA controller on BCM2837 can
> access all RAM that is visible to the ARM cores.

When a device is not cache-coherent and the buffer is not
cache aligned, we now use swiotlb to avoid clobbering data
in the same cache line during DMA synchronization.

We used to rely on kmalloc() returning buffers that are
cacheline aligned, but that was very expensive.

     Arnd