[PATCH v5 6/6] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping

[Nicolin Chen]

On Thu, Jun 06, 2024 at 02:33:02PM +0100, Shameer Kolothum wrote:
> From: Kunkun Jiang <jiangkunkun at huawei.com>
> 
> If io-pgtable quirk flag indicates support for hardware update of
> dirty state, enable HA/HD bits in the SMMU CD and also set the DBM
> bit in the page descriptor.
> 
> Now report the dirty page tracking capability of SMMUv3 and
> select IOMMUFD_DRIVER for ARM_SMMU_V3 if IOMMUFD is enabled.
> 
> Co-developed-by: Keqian Zhu <zhukeqian1 at huawei.com>
> Signed-off-by: Keqian Zhu <zhukeqian1 at huawei.com>
> Signed-off-by: Kunkun Jiang <jiangkunkun at huawei.com>
> Signed-off-by: Joao Martins <joao.m.martins at oracle.com>
> Reviewed-by: Ryan Roberts <ryan.roberts at arm.com>
> Reviewed-by: Jason Gunthorpe <jgg at nvidia.com>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi at huawei.com>

Reviewed-by: Nicolin Chen <nicolinc at nvidia.com>

With a nit:

> +static bool arm_smmu_dbm_capable(struct arm_smmu_device *smmu)
> +{
> +       u32 features = (ARM_SMMU_FEAT_HD | ARM_SMMU_FEAT_COHERENCY);
> +
> +       return (smmu->features & features) == features;

Following the existing coding style in the driver:
	return (smmu->features & ARM_SMMU_FEAT_HD) &&
	       (smmu->features & ARM_SMMU_FEAT_COHERENCY);

And inline?

Thanks
Nicolin