[BOOT-WRAPPER 02/11] aarch64: Remove redundant EL1 entry logic
Mark Rutland
mark.rutland at arm.com
Mon Jul 29 09:14:52 PDT 2024
For historical reasons the boot-wrapper has code to handle being entered
at Non-secure EL1, but currently this is unsupported and cannot be used
to boot a kernel as jump_kernel() unconditionally writes to SCTLR_EL2,
which will UNDEF.
Remove the logic for handling Non-secure EL1.
Signed-off-by: Mark Rutland <mark.rutland at arm.com>
Cc: Akos Denke <akos.denke at arm.com>
Cc: Andre Przywara <andre.przywara at arm.com>
Cc: Luca Fancellu <luca.fancellu at arm.com>
Cc: Marc Zyngier <maz at kernel.org>
---
arch/aarch64/boot.S | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index b889137..51ef41b 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -31,10 +31,8 @@ ASM_FUNC(_start)
b.eq reset_at_el3
cmp x0, #CURRENTEL_EL2
b.eq reset_at_el2
- cmp x0, #CURRENTEL_EL1
- b.eq reset_at_el1
- /* Booting at EL0 is not supported */
+ /* Booting at EL1 or EL0 is not supported */
b .
/*
@@ -72,19 +70,6 @@ reset_at_el2:
msr sctlr_el2, x0
isb
- b reset_no_el3
-
- /*
- * EL1 initialization
- */
-reset_at_el1:
- mov_64 x0, SCTLR_EL1_RESET
- msr sctlr_el1, x0
- isb
-
- b reset_no_el3
-
-reset_no_el3:
cpuid x0, x1
bl find_logical_id
cmp x0, #MPIDR_INVALID
--
2.30.2
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