[PATCH V2 1/3] aarch64: Enable access into SCTLR2_ELx registers from EL2 and below

[Anshuman Khandual]

FEAT_SCTLR2 adds SCTLR2_EL1 and SCTLR2_EL2 system registers. But access
into these register from EL2 and below exception levels, will trap into EL3
unless SCR_EL3.SCTLR2En is set.

Enable access to SCTLR2_ELx registers when they are implemented. Given that
SCTLR2_ELx registers reset to UNKNOWN values - when the highest implemented
exception level is not ELx, this resets SCTLR2_ELx registers. Otherwise any
kernel which is not aware of these SCTLR2_ELx registers, will be subject to
arbitrary behaviour as a result of the SCTLR2_ELx bits which it will not
have configured.

Signed-off-by: Anshuman Khandual <anshuman.khandual at arm.com>
---
 arch/aarch64/include/asm/cpu.h | 7 ++++++-
 arch/aarch64/init.c            | 6 ++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 846b89f..85e735b 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -20,6 +20,9 @@
 #define TCR2_EL2		s3_4_c2_c0_3
 #define TCR2_EL1		s3_0_c2_c0_3
 
+#define SCTLR2_EL1		s3_0_c1_c0_3
+#define SCTLR2_EL2		s3_4_c1_c0_3
+
 /*
  * RES1 bit definitions definitions as of ARM DDI 0487G.b
  *
@@ -56,6 +59,7 @@
 #define SCR_EL3_HXEn			BIT(38)
 #define SCR_EL3_EnTP2			BIT(41)
 #define SCR_EL3_TCR2EN			BIT(43)
+#define SCR_EL3_SCTLR2En		BIT(44)
 #define SCR_EL3_PIEN			BIT(45)
 
 #define HCR_EL2_RES1			BIT(1)
@@ -80,7 +84,8 @@
 
 #define ID_AA64MMFR1_EL1_HCX		BITS(43, 40)
 
-#define ID_AA64MMFR3_EL1_TCRX		BITS(4, 0)
+#define ID_AA64MMFR3_EL1_TCRX		BITS(3, 0)
+#define ID_AA64MMFR3_EL1_SCTLRX		BITS(7, 4)
 #define ID_AA64MMFR3_EL1_S1PIE		BITS(11, 8)
 #define ID_AA64MMFR3_EL1_S2PIE		BITS(15, 12)
 #define ID_AA64MMFR3_EL1_S1POE		BITS(19, 16)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 37cb45f..fc0d2e3 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -89,6 +89,12 @@ void cpu_init_el3(void)
 	if (!kernel_is_32bit())
 		scr |= SCR_EL3_RW;
 
+	if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) {
+		scr |= SCR_EL3_SCTLR2En;
+		msr(SCTLR2_EL2, 0);
+		msr(SCTLR2_EL1, 0);
+	}
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);
-- 
2.25.1