[PATCH 12/13] irqchip/armada-370-xp: Allow mapping only per-CPU interrupts

[Thomas Gleixner]

On Mon, Jul 15 2024 at 12:51, Marek Behún wrote:

> On platforms where MPIC is not the top-level interrupt controller the
> driver currently only supports handling of the per-CPU interrupts (the
> first 29 interrupts). This is obvious from the code of
> mpic_handle_cascade_irq(), where we read only one cause register.

which reads only ....

We read nothing :)

Thanks,

        tglx