mx93: No cache hierachy definitions for ARM cores

[Stefan Wahren]

Am 24.07.24 um 16:34 schrieb Sudeep Holla:
> On Wed, Jul 24, 2024 at 11:48:13AM +0200, Stefan Wahren wrote:
>> Hi Frank,
>>
>> Am 19.07.24 um 16:52 schrieb Frank Li:
>>> On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
>>>> On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst at gmx.net> wrote:
>>>>> Hi,
>>>>> today i noticed that imx93.dtsi lacks the cache definitions for the
>>>>> Cortex-A55 cores:
>>>>>
>>>>> cacheinfo: Unable to detect cache hierarchy for CPU 0
>>>>>
>>>>> Maybe someone with more insight can add this to the imx93.dtsi file.
>>>> Frank, can you help?
>>> Peng:
>>> 	Some informatin missed at public RM. Can you help this? I found
>>> it also missed in internal tree.
>> does the official ARM documentation [1] provide the missing information?
>>
>> [1] - https://developer.arm.com/documentation/101051/0101
> I assume you meant [2] instead of [1], as Cortex A55 and M55 are different.
Sorry, you are absolutely right.
>
> --
> Regards,
> Sudeep
>
> [2] https://developer.arm.com/documentation/100442/0200/